Column redundancy of a multiple block memory architecture

Claim 2

A column redundancy structure of an integrated circuit memory device, comprising: a block of a memory array of the integrated circuit memory device, wherein the block is divided into a plurality of input/output groups with each input/output group of the plurality of input/output groups having a plurality of columns; a plurality of column select multiplexing circuits, with a column select multiplexing circuit of the plurality of column select multiplexing circuits contained within each input/output group of the plurality of input/output groups and with the column select multiplexing circuit coupled to a write bus true, a write bus complement, a read bus true, and a read bus complement; a plurality of redundant column input/output select circuits, with a redundant column input/output select circuit of the plurality of redundant column input/output select circuits contained within each input/output group of the plurality of input/output groups and with the redundant column input/output select circuit coupled to the write bus true, the write bus complement, the read bus true, and the read bus complement; means contained within the column select multiplexing circuit for disabling a bad prime column of the column select multiplexing circuit; and means contained within the redundant column input/output select circuit for enabling a redundant column of the memory array.

Claim 3

The structure of claim 1, wherein the integrated circuit memory device has a multiple block memory architecture and the block is a block of a plurality of blocks.

Claim 4

The structure of claim 1, wherein the means contained within the column select multiplexing circuit for disabling a bad prime column of the column select multiplexing circuit is a fuse circuit and a redundant column signal produced by a redundant column select circuit.

Claim 5

The structure of claim 3, wherein a fuse element of the fuse circuit is removed in order to isolate a bitline pair connected to the bad column from the read bus true, the read bus complement, the write bus true, and the write complement bus of the memory array when the redundant column signal is equal to a first logic state.

Claim 6

The structure of claim 3, wherein the redundant column select circuit comprises: a first fuse element having a first terminal and a second terminal, with the first terminal of the first fuse element coupled to a first voltage supply; a second fuse element having a first terminal and a second terminal; an inverter having a first terminal and a second terminal, with the first terminal of the inverter coupled to the second terminal of the first fuse element; a first logic element having a first input terminal, a second input terminal and an output terminal; a second logic element having a first input terminal, a second input terminal and an output terminal, with the output terminal of the first logic element coupled to the first input terminal of the second logic element; a first transistor, a second transistor, a third transistor, and a fourth transistor, with each transistor have a gate, a first terminal and a second terminal, with a first terminal of the first transistor and a first terminal of the second transistor coupled to the second terminal of the first fuse element; with a gate of the second transistor coupled to a second terminal of the inverter and a second input terminal of the first logic element; with a second terminal of the first transistor, a second terminal of the second transistor, and a second terminal of the fourth transistor coupled to a second supply voltage; a gate of the third transistor coupled to the output terminal of the first logic element; with a first terminal of the third transistor coupled to the first supply voltage; with a second terminal of the third transistor coupled to the second terminal of the second fuse element and the second input terminal of the second logic element; with a first terminal of the fourth transistor coupled to the first terminal of the second fuse element; a power-on reset signal coupled to a gate of the first transistor; an enable signal coupled to a first input terminal of the first logic element; a column select signal coupled to a gate of the fourth transistor; and a redundant column signal produced by the second logic element and coupled to the output terminal of the second logic element.

Claim 7

The structure of claim 1, wherein the means contained within the redundant column input/output select circuit for enabling a redundant column of the memory array is a fuse circuit.

Claim 8

The structure of claim 6, wherein a fuse element of the fuse circuit is left intact to connect a bitline pair connected to the redundant column to the read bus true, the read bus complement, the write bus true, and the write bus complement of the memory array.

Claim 9

The structure of claim 1, wherein the column select multiplexing circuit comprises: a bitline true connected to a first fuse element; a bitline complement connected to a second fuse element; a column select signal; a first transistor, a second transistor, a third transistor, and a fourth transistor, with each transistor having a gate, a first terminal, and a second terminal, with a first terminal of the first transistor coupled to the read bus true, with a second terminal of the first transistor coupled to the first fuse element and a terminal of the third transistor, with a first terminal of the third transistor coupled to the write bus true, with a first terminal of the second transistor coupled to the second fuse element and a first terminal of the fourth transistor, with a second terminal of the second transistor coupled to the read bus complement, and with a second terminal of the fourth transistor coupled to the write bus complement; and a first inverter and a second inverter, with an input terminal of the first inverter coupled to the column select signal, with an output signal of the first inverter coupled to the gate of the first transistor, the gate of the second transistor, and an input terminal of the second inverter, with an output signal of the second inverter coupled to the gate of the third transistor and the gate of the fourth transistor.

Claim 10

The structure of claim 1, wherein the redundant column input/output select circuit comprises: a fuse element having an first terminal and a second terminal; a first inverter and a second inverter, with each inverter having a first terminal and a second terminal; a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, with each transistor having a gate, a first terminal and a second terminal; with a second terminal of the first transistor and a second terminal of the second transistor coupled to a voltage supply, with a first terminal of the first transistor coupled to a first terminal of the second transistor, a second terminal of the fuse element, and a first terminal of the first inverter, with a gate of the second transistor coupled to a second terminal of the first inverter, a first terminal of the second inverter, a gate of the third transistor, and a gate of the fourth transistor, with a second terminal of the second inverter coupled to a gate of the fifth transistor and a gate of the sixth transistor; with a first terminal of the third transistor coupled to the read bus true; with a first terminal of the fourth transistor coupled to the read bus complement; with a second terminal of the third transistor coupled to a first terminal of the fifth transistor and a redundant bitline true; with a first terminal of the fourth transistor coupled to the read bus complement; with a second terminal of the fourth transistor coupled to a first terminal of the sixth transistor and a redundant bitline complement; with a second terminal of the fifth transistor coupled to the write bus true and a second terminal of the sixth transistor coupled to the write bus complement; a redundant column signal coupled to the first terminal of the fuse element; and a power-on reset signal coupled to the gate of the first transistor.

Claim 11

A column redundancy structure of an integrated circuit memory device, comprising: a block of a memory array of the integrated circuit memory device, wherein the block is divided into a plurality of input/output groups with each input/output group of the plurality of input/output groups having a plurality of columns; a plurality of column select multiplexing circuits, with a column select multiplexing circuit of the plurality of column select multiplexing circuits contained within each input/output group of the plurality of input/output groups and with the column select multiplexing circuit coupled to a write bus true, a write bus complement, a read bus true, and a read bus complement, wherein the column select multiplexing circuit further comprises: a bitline true connected to a first fuse element; a bitline complement connected to a second fuse element; a column select signal; a first transistor, a second transistor, a third transistor, and a fourth transistor, with each transistor having a gate, a first terminal, and a second terminal, with a first terminal of the first transistor coupled to the read bus true, with a second terminal of the first transistor coupled to the first fuse element and a terminal of the third transistor, with a first terminal of the third transistor coupled to the write bus true, with a first terminal of the second transistor coupled to the second fuse element and a first terminal of the fourth transistor, with a second terminal of the second transistor coupled to the read bus complement, and with a second terminal of the fourth transistor coupled to the write bus complement; and a first inverter and a second inverter, with an input terminal of the first inverter coupled to the column select signal, with an output signal of the first inverter coupled to the gate of the first transistor, the gate of the second transistor, and an input terminal of the second inverter, with an output signal of the second inverter coupled to the gate of the third transistor and the gate of the fourth transistor; a plurality of redundant column input/output select circuits, with a redundant column input/output select circuit of the plurality of redundant column input/output select circuits contained within each input/output group of the plurality of input/output groups and with the redundant column input/output select circuit coupled to the write bus true, the write bus complement, the read bus true, and the read bus complement, wherein the redundant column input/output select circuit further comprises: a third fuse element having an first terminal and a second terminal; a third inverter and a fourth inverter, with each inverter having a first terminal and a second terminal; a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, with each transistor having a gate, a first terminal and a second terminal; with a second terminal of the fifth transistor and a second terminal of the sixth transistor coupled to a voltage supply, with a first terminal of the fifth transistor coupled to a first terminal of the sixth transistor, a second terminal of the third fuse element, and a first terminal of the third inverter, with a gate of the sixth transistor coupled to a second terminal of the third inverter, a first terminal of the fourth inverter, a gate of the seventh transistor, and a gate of the eighth transistor, with a second terminal of the fourth inverter coupled to a gate of the ninth transistor and a gate of the tenth transistor; with a first terminal of the seventh transistor coupled to the read bus true; with a first terminal of the eighth transistor coupled to the read bus complement; with a second terminal of the seventh transistor coupled to a first terminal of the ninth transistor and a redundant bitline true; with a first terminal of the eighth transistor coupled to the read bus complement; with a second terminal of the eighth transistor coupled to a first terminal of the tenth transistor and a redundant bitline complement; with a second terminal of the ninth transistor coupled to the write bus true; and with a second terminal of the tenth transistor coupled to the write bus complement; a redundant column signal coupled to the first terminal of the third fuse element, wherein the redundant column signal is produced by a redundant column select circuit; and a power-on reset signal coupled to the gate of the fifth transistor.

Claim 12

A column redundancy structure of an integrated circuit memory device, comprising: a block of a memory array of the integrated circuit memory device, wherein the block is divided into a plurality of input/output groups with each input/output group of the plurality of input/output groups having a plurality of columns; a plurality of column select multiplexing circuits, with a column select multiplexing circuit of the plurality of column select multiplexing circuits contained within each input/output group of the plurality of input/output groups and with the column select multiplexing circuit coupled to a write bus true, a write bus complement, a read bus true, and a read bus complement, wherein the column select multiplexing circuit further comprises: a bitline true connected to a first fuse element; a bitline complement connected to a second fuse element; a column select signal; a first transistor, a second transistor, a third transistor, and a fourth transistor, with each transistor having a gate, a first terminal, and a second terminal, with a first terminal of the first transistor coupled to the read bus true, with a second terminal of the first transistor coupled to the first fuse element and a terminal of the third transistor, with a first terminal of the third transistor coupled to the write bus true, with a first terminal of the second transistor coupled to the second fuse element and a first terminal of the fourth transistor, with a second terminal of the second transistor coupled to the read bus complement, and with a second terminal of the fourth transistor coupled to the write bus complement; and a first inverter and a second inverter, with an input terminal of the first inverter coupled to the column select signal, with an output signal of the first inverter coupled to the gate of the first transistor, the gate of the second transistor, and an input terminal of the second inverter, with an output signal of the second inverter coupled to the gate of the third transistor and the gate of the fourth transistor; a plurality of redundant column input/output select circuits, with a redundant column input/output select circuit of the plurality of redundant column input/output select circuits contained within each input/output group of the plurality of input/output groups and with the redundant column input/output select circuit coupled to the write bus true, the write bus complement, the read bus true, and the read bus complement, wherein the redundant column input/output select circuit further comprises: a third fuse element having an first terminal and a second terminal; a third inverter and a fourth inverter, with each inverter having a first terminal and a second terminal; a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, with each transistor having a gate, a first terminal and a second terminal; with a second terminal of the fifth transistor and a second terminal of the sixth transistor coupled to a voltage supply, with a first terminal of the fifth transistor coupled to a first terminal of the sixth transistor, a second terminal of the third fuse element, and a first terminal of the third inverter, with a gate of the sixth transistor coupled to a second terminal of the third inverter, a first terminal of the fourth inverter, a gate of the seventh transistor, and a gate of the eighth transistor, with a second terminal of the fourth inverter coupled to a gate of the ninth transistor and a gate of the tenth transistor; with a first terminal of the seventh transistor coupled to the read bus true; with a first terminal of the eighth transistor coupled to the read bus complement; with a second terminal of the seventh transistor coupled to a first terminal of the ninth transistor and a redundant bitline true; with a first terminal of the eighth transistor coupled to the read bus complement; with a second terminal of the eighth transistor coupled to a first terminal of the tenth transistor and a redundant bitline complement; with a second terminal of the ninth transistor coupled to the write bus true; and with a second terminal of the tenth transistor coupled to the write bus complement; a redundant column signal coupled to the first terminal of the third fuse element, wherein the redundant column signal is produced by a redundant column select circuit; and a power-on reset signal coupled to the gate of the fifth transistor.

Claim 13

The structure of claim 10, wherein the bad prime column of the column select multiplexing circuit is disabled by removing the first fuse element and the second fuse element, thereby isolating the bitline true and the bitline complement from the write bus true, the write bus complement, the read bus true, and the read bus complement.

Claim 14

The structure of claim 10, wherein the redundant column of the memory array is enabled by leaving the third fuse element intact and the redundant bitline true and the redundant bitline complement coupled to the write bus true, the write bus complement, the read bus true, and the read bus complement.

Claim 15

The structure of claim 10, wherein the redundant column select circuit further comprises: a fourth fuse element having a first terminal and a second terminal, with the first terminal of the fourth fuse element coupled to a first voltage supply; a fifth fuse element having a first terminal and a second terminal; a fifth inverter having a first terminal and a second terminal, with the first terminal of the fifth inverter coupled to the second terminal of the fourth fuse element; a first logic element having a first input terminal, a second input terminal and an output terminal; a second logic element having a first input terminal, a second input terminal and an output terminal, with the output terminal of the first logic element coupled to the first input terminal of the second logic element; a eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, with each transistor have a gate, a first terminal and a second terminal, with a first terminal of the eleventh transistor and a first terminal of the twelfth transistor coupled to the second terminal of the fourth fuse element; with a gate of the twelfth transistor coupled to a second terminal of the fifth inverter and a second input terminal of the first logic element; with a second terminal of the eleventh transistor, a second terminal of the twelfth transistor, and a second terminal of the fourteenth transistor coupled to a second supply voltage; a gate of the thirteenth transistor coupled to the output terminal of the first logic element; with a first terminal of the thirteenth transistor coupled to the first supply voltage; with a second terminal of the thirteenth transistor coupled to the output terminal of the first logic element; with a first terminal of the thirteenth transistor coupled to the first supply voltage; with a second terminal of the thirteenth transistor coupled to the second terminal of the fifth fuse element and the second input terminal of the second logic element; with a first terminal of the fourteenth transistor coupled to the first terminal of the fifth fuse element; a power-on reset signal coupled to a gate of the eleventh transistor; an enable signal coupled to a first input terminal of the first logic element; a column select signal coupled to a gate of the fourteenth transistor; and a redundant column signal produced by the second logic element and coupled to the output terminal of the second logic element.

Claim 16

The structure of claim 10, wherein the integrated circuit memory device has a multiple block memory architecture and the block is a block of a plurality of blocks.

Claim 17

A column redundancy structure of an integrated circuit memory device, comprising: a block of a memory array of the integrated circuit memory device, wherein the block is divided into a plurality of input/output groups with each input/output group of the plurality of input/output groups having a plurality of columns; a plurality of redundant column input/output select circuits, with a redundant column input/output select circuit of the plurality of redundant column input/output select circuits contained within each input/output group of the plurality of input/output groups and with the redundant column input/output select circuit coupled to a write bus true, a write bus complement, a read bus true, and a read bus complement, wherein the redundant column input/output select circuit further comprises: a first fuse element having an first terminal and a second terminal; a first inverter and a second inverter, with each inverter having a first terminal and a second terminal; a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, with each transistor having a gate, a first terminal and a second terminal; with a second terminal of the first transistor and a second terminal of the second transistor coupled to a voltage supply, with a first terminal of the first transistor coupled to a first terminal of the second transistor, a second terminal of the first fuse element, and a first terminal of the first inverter, with a gate of the second transistor coupled to a second terminal of the first inverter, a first terminal of the second inverter, a gate of the third transistor, and a gate of the fourth transistor, with a second terminal of the second inverter coupled to a gate of the fifth transistor and a gate of the sixth transistor; with a first terminal of the third transistor coupled to the read bus true; with a first terminal of the fourth transistor coupled to the read bus complement; with a second terminal of the third transistor coupled to a first terminal of the fifth transistor and a redundant bitline true; with a first terminal of the fourth transistor coupled to the read bus complement; with a second terminal of the fourth transistor coupled to a first terminal of the sixth transistor and a redundant bitline complement; with a second terminal of the fifth transistor coupled to the write bus true and a second terminal of the sixth transistor coupled to the write bus complement; a redundant column signal coupled to the first terminal of the first fuse element; and a power-on reset signal coupled to the gate of the first transistor.

Claim 18

A column redundancy structure of an integrated circuit memory device, comprising: a block of a memory array of the integrated circuit memory device, wherein the block is divided into a plurality of input/output groups with each input/output group of the plurality of input/output groups having a plurality of columns; a plurality of redundant column input/output select circuits, with a redundant column input/output select circuit of the plurality of redundant column input/output select circuits contained within each input/output group of the plurality of input/output groups and with the redundant column input/output select circuit coupled to a write bus true, a write bus complement, a read bus true, and a read bus complement, wherein the redundant column input/output select circuit further comprises: a first fuse element having an first terminal and a second terminal; a first inverter and a second inverter, with each inverter having a first terminal and a second terminal; a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, with each transistor having a gate, a first terminal and a second terminal; with a second terminal of the first transistor and a second terminal of the second transistor coupled to a voltage supply, with a first terminal of the first transistor coupled to a first terminal of the second transistor, a second terminal of the first fuse element, and a first terminal of the first inverter, with a gate of the second transistor coupled to a second terminal of the first inverter, a first terminal of the second inverter, a gate of the third transistor, and a gate of the fourth transistor, with a second terminal of the second inverter coupled to a gate of the fifth transistor and a gate of the sixth transistor; with a first terminal of the third transistor coupled to the read bus true; with a first terminal of the fourth transistor coupled to the read bus complement; with a second terminal of the third transistor coupled to a first terminal of the fifth transistor and a redundant bitline true; with a first terminal of the fourth transistor coupled to the read bus complement; with a second terminal of the fourth transistor coupled to a first terminal of the sixth transistor and a redundant bitline complement; with a second terminal of the fifth transistor coupled to the write bus true and a second terminal of the sixth transistor coupled to the write bus complement; a redundant column signal coupled to the first terminal of the first fuse element; and a power-on reset signal coupled to the gate of the first transistor.

Claim 19

The structure of claim 15, wherein the integrated circuit memory device has a multiple block memory architecture and the block is a block of a plurality of blocks.

Claim 20

The structure of claim 15, wherein the redundant column of the memory array is enabled by leaving the first fuse element intact and the redundant bitline true and the redundant bitline complement coupled to the write bus true, the write bus complement, the read bus true, and the read bus complement.

Claim 21

The structure of claim 15, wherein the redundant column signal is produced by a redundant column select circuit which comprises: a second fuse element having a first terminal and a second terminal, with the first terminal of the second fuse element coupled to a first voltage supply; a third fuse element having a first terminal and a second terminal; a third inverter having a first terminal and a second terminal, with the first terminal of the third inverter coupled to the second terminal of the second fuse element; a first logic element having a first input terminal, a second input terminal and an output terminal; a second logic element having a first input terminal, a second input terminal and an output terminal, with the output terminal of the first logic element coupled to the first input terminal of the second logic element; a seventh transistor, a eighth transistor, a ninth transistor, and a tenth transistor, with each transistor have a gate, a first terminal and a second terminal, with a first terminal of the seventh transistor and a first terminal of the eighth transistor coupled to the second terminal of the second fuse element; with a gate of the eighth transistor coupled to a second terminal of the third inverter and a second input terminal of the first logic element; with a second terminal of the seventh transistor, a second terminal of the eighth transistor, and a second terminal of the tenth transistor coupled to a second supply voltage; a gate of the ninth transistor coupled to the output terminal of the first logic element; with a first terminal of the ninth transistor coupled to the first supply voltage; with a second terminal of the ninth transistor coupled to the second terminal of the third fuse element and the second input terminal of the second logic element; with a first terminal of the tenth transistor coupled to the first terminal of the third fuse element; a power-on reset signal coupled to a gate of the seventh transistor; an enable signal coupled to a first input terminal of the first logic element; a column select signal coupled to a gate of the tenth transistor; and a redundant column signal produced by the second logic element and coupled to the output terminal of the second logic element.