US5608677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Boosting voltage circuit used in active cycle of a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
•
Filing: 1995-12-28
•
Granted: 1997-03-04
•
Expires: 2015-12-28
Abstract
Abstract A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.
Inventors
- 👤 Sei-Seung Yoon
- 👤 Chan-Jong Park
- 👤 Byung-Chul Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:46
CPC Classifications
G; G11; G11B; G11B17/00; G11B17/02; G11C; G11C5/00; G11C5/14; G11C5/145; G11B19/00; G11B19/20; G11B2220/00; G11B2220/20; G11B2220/25; G11B2220/2537; G11B2220/2545
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
192 words
A voltage boosting circuit for a semiconductor memory device comprising: first circuit means for supplying a chip master clock determining an active state and stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of said chip master clock is generated, and for generating a latch control signal a second delay time after the first state of said chip master clock is generated, said detector control signal having a first pulse width and said latch control signal having a second pulse width; second circuit means for responding to said detector control signal and said latch control signal and generating a detecting signal indicative of a current state of a boosting voltage potential; third circuit means for generating a boosting voltage generator control signal activated in response to said chip master clock and timed to occur simultaneously with said detecting signal; and first and second boosting voltage generating means for generating said boosting voltage potential, respectively operating in said stand-by state and said active state in accordance with said detecting signal and said boosting voltage generator control signal.
Claim 2
Dependent Claim
192 words
A voltage boosting circuit for a semiconductor memory device comprising: first circuit means for supplying a chip master clock determining an active state and stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of said chip master clock is generated, and for generating a latch control signal a second delay time after the first state of said chip master clock is generated, said detector control signal having a first pulse width and said latch control signal having a second pulse width; second circuit means for responding to said detector control signal and said latch control signal and generating a detecting signal indicative of a current state of a boosting voltage potential; third circuit means for generating a boosting voltage generator control signal activated in response to said chip master clock and timed to occur simultaneously with said detecting signal; and first and second boosting voltage generating means for generating said boosting voltage potential, respectively operating in said stand-by state and said active state in accordance with said detecting signal and said boosting voltage generator control signal.
Claim 3
Dependent Claim
219 words
A boosting voltage circuit of a semiconductor memory device comprising: first circuit means for supplying a chip master clock determining an active state and stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of said chip master clock is generated, and for generating a latch control signal a second delay time after the first state of said chip master clock is generated, said detector control signal having a first pulse width and said latch control signal having a second pulse width; second circuit means for responding to said detector control signal and said latch control signal and generating a first detecting signal indicative of a current state of a boosting voltage potential; third circuit means responsive to said first detecting signal and generating a second detecting signal in accordance with the control of said chip master clock; fourth circuit means for generating a boosting voltage generator control signal activated in response to said chip master clock and timed to occur simultaneously with said second detecting signal; and first and second boosting voltage generating means for generating said boosting voltage potential, respectively operating in said stand-by state and said active state in accordance with said detecting signal and said boosting voltage generator control signal.
Claim 4
Dependent Claim
219 words
A boosting voltage circuit of a semiconductor memory device comprising: first circuit means for supplying a chip master clock determining an active state and stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of said chip master clock is generated, and for generating a latch control signal a second delay time after the first state of said chip master clock is generated, said detector control signal having a first pulse width and said latch control signal having a second pulse width; second circuit means for responding to said detector control signal and said latch control signal and generating a first detecting signal indicative of a current state of a boosting voltage potential; third circuit means responsive to said first detecting signal and generating a second detecting signal in accordance with the control of said chip master clock; fourth circuit means for generating a boosting voltage generator control signal activated in response to said chip master clock and timed to occur simultaneously with said second detecting signal; and first and second boosting voltage generating means for generating said boosting voltage potential, respectively operating in said stand-by state and said active state in accordance with said detecting signal and said boosting voltage generator control signal.
Claim 5
Dependent Claim
162 words
A voltage boosting circuit for a semiconductor memory device comprising: a clock generator for supplying a chip master clock determining an active state and stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of said chip master clock is generated, and for generating a latch control signal a second delay time after the first state of said chip master clock is generated, said detector control signal having a first pulse width and said latch control signal having a second pulse width; a boosting voltage detector for responding to said detector control signal and said latch control signal and generating a detecting signal indicative of a current state of a boosting voltage potential; first and second boosting voltage generators for generating said boosting voltage potential, respectively operating in said stand-by state and active state in accordance with said detecting signal and delayed said chip master clock signal.
Claim 6
Dependent Claim
162 words
A voltage boosting circuit for a semiconductor memory device comprising: a clock generator for supplying a chip master clock determining an active state and stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of said chip master clock is generated, and for generating a latch control signal a second delay time after the first state of said chip master clock is generated, said detector control signal having a first pulse width and said latch control signal having a second pulse width; a boosting voltage detector for responding to said detector control signal and said latch control signal and generating a detecting signal indicative of a current state of a boosting voltage potential; first and second boosting voltage generators for generating said boosting voltage potential, respectively operating in said stand-by state and active state in accordance with said detecting signal and delayed said chip master clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |