Circuitry with gate line crossing semiconductor line at two or more channels

Claim 2

A product comprising: a substrate with a surface at which circuitry can be formed; and circuitry formed at the surface of the substrate; the circuitry comprising: a first line extending between first and second connecting points at which the first line is electrically connected to other components; the first line being in a first layer of the circuitry; the first layer comprising semiconductor material; a second line in a second layer of the circuitry; and a third line providing a gate signal; the second line being connected to receive the gate signal from the third line at a first end of the second line; the second line extending with a substantially constant width along a length from the first end to a second end; the second line crossing the first line in channel regions at least twice along its length between the first and second ends; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line conducting the gate signal to all of the channel regions; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 3

The product of claim 1 in which the substrate is an insulating substrate.

Claim 4

The product of claim 1 in which the circuitry is thin film circuitry.

Claim 5

The product of claim 1 in which the second layer of the circuitry comprises semiconductor material.

Claim 6

The product of claim 4 in which the second layer comprises polysilicon.

Claim 7

The product of claim 1 in which the first layer comprises polysilicon.

Claim 8

The product of claim 1 in which the first line comprises a first density of charge carrier sources and destinations in the channel regions and a second density of charge carrier sources and destinations in areas other than the channel regions; the second density being much greater than the first density.

Claim 9

The product of claim 1, further comprising an insulating layer between the first and second layers in each of the channel regions.

Claim 10

The product of claim 1 in which the channel regions are substantially the same in size and shape.

Claim 11

The product of claim 1 in which the first line has a first width in each channel region and the second line has a second width in each channel region; the first and second widths being approximately equal.

Claim 12

The product of claim 1 in which each channel region is rectangular, the first line and the second line being perpendicular in each channel region.

Claim 13

A product comprising: a substrate with a surface at which circuitry can be formed; and circuitry formed at the surface of the substrate; the circuitry comprising: a first line extending between first and second connecting points at which the first line is electrically connected to other components; the first line being in a first layer of the circuitry; the first layer comprising semiconductor material; a second line in a second layer of the circuitry; the second line being connected to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the second layer of the circuitry comprising polysilicon semiconductor material; and a third line in a third layer of the circuitry; the third layer comprising conductive metal; the third line providing the gate signal; the second line having an end electrically connected to the third line; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 14

A product comprising: a substrate with a surface at which circuitry can be formed; and circuitry formed at the surface of the substrate; the circuitry comprising: a first line extending between first and second connecting points at which the first line is electrically connected to other components; the first line being in a first layer of the circuitry; the first layer comprising semiconductor material; a second line in a second layer of the circuitry; the second line being connected to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the second layer of the circuitry comprising polysilicon semiconductor material; and a third line in a third layer of the circuitry; the third layer comprising conductive metal; the third line providing the gate signal; the second line having an end electrically connected to the third line; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 15

A product comprising: a substrate with a surface at which circuitry can be formed; and circuitry formed at the surface of the substrate; the circuitry comprising: a first line extending between first and second connecting points at which the first line is electrically connected to other components; the first line being in a first layer of the circuitry; the first layer comprising semiconductor material; a second line in a second layer of the circuitry; the second line being connected to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the second layer of the circuitry comprising conductive metal; and a third line in the second layer; the third line providing the gate signal; the second and third lines being electrically connected; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 16

A product comprising: a substrate with a surface at which circuitry can be formed; and circuitry formed at the surface of the substrate; the circuitry comprising: a first line extending between first and second connecting points at which the first line is electrically connected to other components; the first line being in a first layer of the circuitry; the first layer comprising semiconductor material; a second line in a second layer of the circuitry; the second line being connected to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the second layer of the circuitry comprising conductive metal; and a third line in the second layer; the third line providing the gate signal; the second and third lines being electrically connected; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 17

A product comprising: a substrate with a surface at which circuitry can be formed; and circuitry formed at the surface of the substrate; the circuitry comprising: a first line extending between first and second connecting points at which the first line is electrically connected to other components; the first line being in a first layer of the circuitry; the first layer comprising semiconductor material; a second line in a second layer of the circuitry; the second line being connected to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the first and second lines crossing in first and second channel regions, the first line extending in a first direction through the first channel region and in a second direction perpendicular to the first direction through the second channel region; the second line extending in the first direction through the second channel region and in the second direction through the first channel region; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 18

A product comprising: a substrate with a surface at which circuitry can be formed; and circuitry formed at the surface of the substrate; the circuitry comprising: a first line extending between first and second connecting points at which the first line is electrically connected to other components; the first line being in a first layer of the circuitry; the first layer comprising semiconductor material; a second line in a second layer of the circuitry; the second line being connected to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the first and second lines crossing in first and second channel regions, the first line extending in a first direction through the first channel region and in a second direction perpendicular to the first direction through the second channel region; the second line extending in the first direction through the second channel region and in the second direction through the first channel region; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 19

The product of claim 14 in which each of the first and second lines includes an angle of approximately 90° between the first and second channel regions.

Claim 20

An array comprising: a substrate with a surface at which circuitry can be formed; and array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of M scan lines, where M is greater than 1; each of the scan lines extending approximately in a first direction across the surface of the substrate; the M scan lines being positioned in order from first through Mth; a set of N data lines, where N is greater than 1; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being different than the first direction; the N data lines being positioned in order from first through Nth; for each value of m from 1 through M and for each value of n from 1 through N, a crossing region in which the mth scan line and the nth data line cross; for each of a set of one or more of the crossing regions, cell circuitry connected to the mth scan line and the nth data line; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from or providing signals to the nth data line; a first line extending between a first connecting point at which the first line is electrically connected to the nth data line and a second connecting point at which the first line is electrically connected to the data lead of the component; the first line being in a first layer of the array circuitry; the first layer comprising semiconductor material; and a second line in a second layer of the array circuitry; the second line being connected to receive a gate signal from the mth scan line; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 21

An array comprising: a substrate with a surface at which circuitry can be formed; and array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of M scan lines, where M is greater than 1; each of the scan lines extending approximately in a first direction across the surface of the substrate; the M scan lines being positioned in order from first through Mth; a set of N data lines, where N is greater than 1; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being different than the first direction; the N data lines being positioned in order from first through Nth; for each value of m from 1 through M and for each value of n from 1 through N, a crossing region in which the mth scan line and the nth data line cross; for each of a set of one or more of the crossing regions, cell circuitry connected to the mth scan line and the nth data line; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from or providing signals to the nth data line; a first line extending between a first connecting point at which the first line is electrically connected to the nth data line and a second connecting point at which the first line is electrically connected to the data lead of the component; the first line being in a first layer of the array circuitry; the first layer comprising semiconductor material; and a second line in a second layer of the array circuitry; the second line being connected to receive a gate signal from the mth scan line; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line.

Claim 22

The array of claim 16 in which the mth scan line comprises aluminum.

Claim 23

The array of claim 16 in which the component comprises a capacitive element.

Claim 24

The array of claim 16 in which the mth and (m+1)th scan lines and the nth and (n+1)th data lines bound a cell area; the component comprising a cell electrode in the cell area; the cell electrode being connected to the data lead.

Claim 25

The array of claim 19 in which the cell electrode is light transmissive.

Claim 26

The array of claim 16 in which the nth data line has a width in the first direction between first and second edges and the channel regions are between the first and second edges.

Claim 27

The array of claim 21 in which the first line is between the nth data line and the substrate.

Claim 28

The array of claim 21 in which the second line is substantially all between the first and second edges; the second line being connected to the mth scan line in the crossing region.

Claim 29

A display comprising: a substrate with a surface at which circuitry can be formed; array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of M scan lines, where M is greater than 1; each of the scan lines extending approximately in a first direction across the surface of the substrate; the M scan lines being positioned in order from first through Mth; a set of N data lines, where N is greater than 1; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being different than the first direction; the N data lines being positioned in order from first through Nth; for each value of m from 1 through M and for each value of n from 1 through N, a crossing region in which the mth scan line and the nth data line cross; for each of a set of one or more of the crossing regions, cell circuitry connected to the mth scan line and the nth data line; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from the nth data line; the mth and (m+1)th scan lines and the nth and (n+1)th data lines bounding a cell area; the component comprising a light transmissive cell electrode in the cell area; the cell electrode being connected for receiving signals from the data lead; a first line extending between a first connecting point at which the first line is electrically connected to the nth data line and a second connecting point at which the first line is electrically connected to the data lead of the component; the first line being in a first layer of the array circuitry; the first layer comprising semiconductor material; and a second line in a second layer of the array circuitry; the second line being electrically connected to the mth scan line to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line; and a liquid crystal material positioned along the cell electrode so that data signals received by the cell electrode from the nth data line control light transmissivity of the liquid crystal material; the data signals being received from the nth data line under control of the gate signal from the mth scan line.

Claim 30

A display comprising: a substrate with a surface at which circuitry can be formed; array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of M scan lines, where M is greater than 1; each of the scan lines extending approximately in a first direction across the surface of the substrate; the M scan lines being positioned in order from first through Mth; a set of N data lines, where N is greater than 1; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being different than the first direction; the N data lines being positioned in order from first through Nth; for each value of m from 1 through M and for each value of n from 1 through N, a crossing region in which the mth scan line and the nth data line cross; for each of a set of one or more of the crossing regions, cell circuitry connected to the mth scan line and the nth data line; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from the nth data line; the mth and (m+1)th scan lines and the nth and (n+1)th data lines bounding a cell area; the component comprising a light transmissive cell electrode in the cell area; the cell electrode being connected for receiving signals from the data lead; a first line extending between a first connecting point at which the first line is electrically connected to the nth data line and a second connecting point at which the first line is electrically connected to the data lead of the component; the first line being in a first layer of the array circuitry; the first layer comprising semiconductor material; and a second line in a second layer of the array circuitry; the second line being electrically connected to the mth scan line to receive a gate signal; the second line crossing the first line in two or more channel regions; the first line including a channel in each channel region, the channels being in series between the first and second connecting points; the second line being conductive so that the second line conducts the gate signal to all of the channel regions; the first line including charge carrier sources and destinations positioned so that conductivity of the first line between the first and second connecting points is controlled by the gate signal conducted to the channel regions by the second line; and a liquid crystal material positioned along the cell electrode so that data signals received by the cell electrode from the nth data line control light transmissivity of the liquid crystal material; the data signals being received from the nth data line under control of the gate signal from the mth scan line.