Flat panel display interface for a high resolution computer graphics system

Claim 2

A graphics circuit for driving one of a cathode ray tube ("CRT") display and a flat panel display, said graphics circuit comprising: a CRT connector for coupling the CRT display to the graphics circuit; a flat panel connector for coupling the flat panel display to the graphics circuit; a frame buffer which contains at least a set of digital pixel data; a processor coupled to said CRT connector and said frame buffer, said processor senses said CRT connector to determine whether the CRT display is coupled to said CRT connector and transmits at least said set of digital pixel data to said frame buffer; a ramdac circuit coupled to said processor and said frame buffer, said ramdac circuit includes circuitry that generates a set of video sync signals for the CRT display, circuitry that performs a color look-up table function on a pixel data stream provided by said frame buffer to produce a color pixel data stream, if the flat panel display is coupled to the graphics circuit and is color or the CRT display is coupled to the graphics circuit, circuitry that generates a set of analog video signals based on the color pixel data stream and said set of video sync signals, if the CRT display is coupled to the graphics circuit, and circuitry that bypasses the color look-up table function on the pixel data stream, if the flat panel display is coupled to the graphics circuit and is monochrome; and a color buffer circuit coupled to said ramdac circuit, said flat panel connector and said processor, said color buffer circuit includes circuitry that automatically senses whether (i) the flat panel display is coupled to the graphics circuit and (ii) the flat panel display is color or monochrome, circuitry that converts the set of video sync signals into a set of color flat panel sync signals, if the flat panel display is coupled to the graphics circuit and is color, and circuitry that converts the video sync signals into a set of monochrome flat panel sync signals, if the flat panel display is coupled to the graphics circuit and is monochrome.

Claim 3

The graphics circuit of claim 1, wherein the color buffer circuit includes circuitry that receives the color pixel data stream from the ramdac circuit and that generates a color digital data stream by synchronizing the color pixel data stream to the color flat panel sync signals, if the flat panel display is coupled to the graphics circuit and is color.

Claim 4

The graphics circuit of claim 2, wherein the circuitry that generates the color digital data stream synchronized by the color flat panel sync signals includes circuitry that demultiplexes the color pixel data stream, if the flat panel display is coupled to the graphics circuit and is color.

Claim 5

The graphics circuit of claim 1, wherein the color buffer circuit includes circuitry that receives the pixel data stream from the ramdac circuit and that generates a monochrome digital data stream by synchronizing the pixel data stream to the monochrome flat panel sync signals, if the flat panel display is coupled to the graphics circuit and is monochrome.

Claim 6

The graphics circuit of claim 1, wherein the ramdac circuit includes an analog pixel output port coupled to transfer the set of analog video signals to the CRT display.

Claim 7

The graphics circuit of claim 1, wherein the pixel data stream defines an image for display on the flat panel display or the CRT display.

Claim 8

The graphics circuit of claim 1, wherein the ramdac circuit includes a digital pixel output port coupled to transfer the pixel data stream to the color buffer circuit.

Claim 9

The graphics circuit of claim 1, wherein the color buffer circuit further includes circuitry for sensing a pixel resolution of the flat panel display, if the flat panel display is coupled to the graphics circuit.

Claim 12

The method of claim 9, wherein the step of performing a color look-up table function includes the steps of generating a color digital data stream by synchronizing the pixel data stream to the color flat panel sync signals and transferring the color digital data stream and the color flat panel sync signals to the flat panel display, if the flat panel display is color.

Claim 13

The method of claim 10, wherein the step of generating a color digital data stream includes the step of demultiplexing the pixel data stream, if the flat panel display is color.

Claim 14

The method of claim 9, wherein the step of bypassing the color look-up table function includes the steps of generating a monochrome digital data stream by synchronizing the pixel data stream to the monochrome flat panel sync signals and transferring the monochrome digital data stream and the monochrome flat panel sync signals to the flat panel display, if the flat panel display is monochrome.

Claim 15

The method of claim 9, wherein if the CRT display is sensed to be coupled to the graphics subsystem, the method further comprises the step of generating a set of analog video signals for the CRT display by performing the color look-up table function on the pixel data stream to produce a color pixel data stream and by performing a digital to analog conversion function on the color pixel data stream.

Claim 16

The method of claim 9 further comprising the step of transferring the analog video signals and the video sync signals to the CRT display.

Claim 17

The method of claim 9 further comprising the step of receiving the pixel data stream from a frame buffer that stores an image for display on the flat panel display or the CRT display.

Claim 18

The method of claim 9, wherein after the step of sensing whether the flat panel display is color or monochrome, the method further comprises the step of sensing a pixel resolution of the flat panel display.

Claim 19

A computer system comprising: a processor that generates a set of graphics data that defines an image for display on a flat panel display or a cathode ray tube ("CRT") display; and a graphics subsystem coupled to the processor, the graphics subsystem includes a frame buffer, a rendering processor coupled to the processor and the frame buffer, the rendering processor receives the graphics data from the processor, converts the graphics data into digital pixel data and transfers the digital pixel data into the frame buffer, the rendering processor further automatically senses information, subsequently read by the processor, as to whether the CRT display is coupled to the graphics subsystem, a ramdac circuit coupled to the frame buffer and the rendering processor, the ramdac circuit includes circuitry that generates a set of video sync signals for the CRT display, circuitry that performs a color look-up table function on a pixel data stream read from the frame buffer to produce a color pixel data stream, if the flat panel display is coupled to the graphics subsystem and is color or the CRT display is coupled to the graphics subsystem, circuitry that generates a set of analog video signals based on the color pixel data stream and the set of video sync signals, if the CRT display is coupled to the graphics subsystem, and circuitry that bypasses the color look-up table function on the pixel data stream if the flat panel display is coupled to the graphics subsystem and is monochrome, and a color buffer circuit coupled to said ramdac circuit, said flat panel connector, said rendering processor and said processor, said color buffer circuit including circuitry that senses whether the flat panel display is coupled to the graphics subsystem and whether the flat panel display is color or monochrome, said circuitry is read by the processor, circuitry that converts the set of video sync signals into a set of color flat panel sync signals, if the flat panel display is coupled to the graphics subsystem and is color, and circuitry that converts the set of video sync signals into a set of monochrome flat panel sync signals, if the flat panel display is coupled to the graphics subsystem and is monochrome.

Claim 20

A computer system comprising: a processor that generates a set of graphics data that defines an image for display on a flat panel display or a cathode ray tube ("CRT") display; and a graphics subsystem coupled to the processor, the graphics subsystem includes a frame buffer, a rendering processor coupled to the processor and the frame buffer, the rendering processor receives the graphics data from the processor, converts the graphics data into digital pixel data and transfers the digital pixel data into the frame buffer, the rendering processor further automatically senses information, subsequently read by the processor, as to whether the CRT display is coupled to the graphics subsystem, a ramdac circuit coupled to the frame buffer and the rendering processor, the ramdac circuit includes circuitry that generates a set of video sync signals for the CRT display, circuitry that performs a color look-up table function on a pixel data stream read from the frame buffer to produce a color pixel data stream, if the flat panel display is coupled to the graphics subsystem and is color or the CRT display is coupled to the graphics subsystem, circuitry that generates a set of analog video signals based on the color pixel data stream and the set of video sync signals, if the CRT display is coupled to the graphics subsystem, and circuitry that bypasses the color look-up table function on the pixel data stream if the flat panel display is coupled to the graphics subsystem and is monochrome, and a color buffer circuit coupled to said ramdac circuit, said flat panel connector, said rendering processor and said processor, said color buffer circuit including circuitry that senses whether the flat panel display is coupled to the graphics subsystem and whether the flat panel display is color or monochrome, said circuitry is read by the processor, circuitry that converts the set of video sync signals into a set of color flat panel sync signals, if the flat panel display is coupled to the graphics subsystem and is color, and circuitry that converts the set of video sync signals into a set of monochrome flat panel sync signals, if the flat panel display is coupled to the graphics subsystem and is monochrome.

Claim 21

The computer system of claim 17, wherein the color buffer circuit includes circuitry that receives the color pixel data stream from the ramdac circuit and that generates a color digital data stream by synchronizing the color pixel data stream to the color flat panel sync signals, if the flat panel display is coupled to the graphics subsystem and is color.

Claim 22

The computer system of claim 18, wherein the circuitry that generates the color digital data stream synchronized by the color flat panel sync signals includes circuitry that demultiplexes the color pixel data stream, if the flat panel display is coupled to the graphics subsystem and is color.

Claim 23

The computer system of claim 17, wherein the color buffer circuit includes circuitry that receives the pixel data stream from the ramdac circuit and that generates a monochrome digital data stream by synchronizing the pixel data stream to the monochrome flat panel sync signals, if the flat panel display is coupled to the graphics subsystem and is monochrome.

Claim 24

The computer system of claim 17, wherein the circuitry that generates the set of analog video signals for the CRT display perform the color look-up table function to produce the color pixel data stream and a digital to analog conversion function on the color pixel data stream.

Claim 25

The computer system of claim 17, wherein the ramdac circuit includes an analog pixel output port coupled to transfer the analog video signals to the CRT display.

Claim 26

The computer system of claim 17, wherein the ramdac circuit includes a digital pixel output port coupled to transfer the pixel data stream to the color buffer circuit.

Claim 27

The computer system of claim 17, wherein the color buffer circuit includes circuitry that senses a pixel resolution of the flat panel display, if the flat panel display is coupled to the graphics subsystem.