US5606529A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor disk storage
Assignee: Samsung Electronics Co Ltd
•
Filing: 1996-03-06
•
Granted: 1997-02-25
•
Expires: 2016-03-06
Abstract
Abstract A semiconductor storage device transfers data with an information processing device and includes a non-volatile semiconductor memory in which data is electrically re-writable, a volatile semiconductor memory connected to the non-volatile memory and temporarily storing data of the non-volatile semiconductor memory, and a CPU connected to the volatile semiconductor memory and the non-volatile semiconductor memory. The CPU controls the transfer of data among the non-volatile memory, the volatile memory and the CPU. The CPU also transfers data with the information processing device in accordance with a fixed-length form for data. When an access from the CPU to the volatile semiconductor makes a miss hit (i.e., misses), the CPU accesses the non-volatile semiconductor memory. When a failure is generated in the non-volatile semiconductor memory or when a predicted service life of the non-volatile semiconductor memory is elapsed, the non-volatile semiconductor memory can be substituted by an alternate memory.
Inventors
- 👤 Hisao Honma
- 👤 Kazuo Nakagoshi
- 👤 Naoya Takahashi
- 👤 Makoto Kogai
- 👤 Kenichi Takamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:41
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0866; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022; G06F2212/31; G06F2212/312; G06F3/0628; G06F3/0662; G06F3/0664
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
118 words
A semiconductor storage device for transferring data with an information processing device, said semiconductor storage device comprising: a non-volatile semiconductor memory in which data is electrically rewritable; a volatile semiconductor memory connected to said non-volatile semiconductor memory and temporarily storing data of said non-volatile semiconductor memory; and a CPU coupled to said non-volatile semiconductor memory and said volatile semiconductor memory, said CPU controlling a transfer of data among said non-volatile semiconductor memory, said volatile semiconductor memory, and said CPU; wherein said CPU transfers data with said information processing device in accordance with a fixed-length form for data and, when an access from said CPU to said volatile semiconductor memory makes a miss hit, accesses said non-volatile semiconductor memory.
Claim 2
Dependent Claim
118 words
A semiconductor storage device for transferring data with an information processing device, said semiconductor storage device comprising: a non-volatile semiconductor memory in which data is electrically rewritable; a volatile semiconductor memory connected to said non-volatile semiconductor memory and temporarily storing data of said non-volatile semiconductor memory; and a CPU coupled to said non-volatile semiconductor memory and said volatile semiconductor memory, said CPU controlling a transfer of data among said non-volatile semiconductor memory, said volatile semiconductor memory, and said CPU; wherein said CPU transfers data with said information processing device in accordance with a fixed-length form for data and, when an access from said CPU to said volatile semiconductor memory makes a miss hit, accesses said non-volatile semiconductor memory.
Claim 3
Dependent Claim
170 words
A semiconductor storage device according to claim 1, further comprising: at least one alternate memory board having a storage capacity smaller than that of said non-volatile semiconductor memory; a data control circuit connected to said CPU, said non-volatile semiconductor memory, and said volatile semiconductor memory and said alternate memory board for making data communication with said information processing device in accordance with an instruction from said CPU; and wherein in accordance with an instruction from a ROM connected to said CPU and storing a program for access control for said non-volatile semiconductor memory and said volatile semiconductor memory corresponding to an access request from said information processing device and when the number of times of writing into one board of said non-volatile semiconductor memory reaches a predetermined number of times, said CPU causes said data control circuit to make a change in control so that data of said one board is transferred to said at least one alternate memory board and subsequent access is made to said alternate memory board.
Claim 4
Dependent Claim
52 words
A semiconductor storage device according to claim 2, wherein each of said at least one alternate memory board and the board of said non-volatile semiconductor memory is provided with a pilot lamp, and said CPU lights the pilot lamp of said one board for which said predetermined number of times is reached.
Claim 5
Dependent Claim
64 words
A semiconductor storage device according to claim 2, wherein said data control circuit translates a logical block number included in the access request received from said information processing device into a block number and a sub-block number in accordance with a predetermined operation so that the transfer of data between said data control circuit and a cache memory is made in a fixed-length form.
Claim 6
Dependent Claim
49 words
A semiconductor storage device according to claim 4, wherein said data control circuit makes the transfer of data between said data control circuit and a flash memory in a fixed-length form on the basis of said block number the unit of which is composed of a plurality of sub-blocks.
Claim 7
Dependent Claim
49 words
A semiconductor storage device according to claim 4, wherein said ROM stores interface data for data accessed between said information processing device and said data control circuit, and said data control circuit makes the transfer of data for said information processing device on the basis of said interface data.
Claim 8
Dependent Claim
21 words
A semiconductor storage device according to claim 6, wherein said ROM stores interface data of either of SCSI, PC/AT, and PCMCIA.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |