Memory controller for sub-memory unit such as disk drives

Claim 1

A controller coupled to a host system, an external storage unit and a temporary memory for performing a data transfer thereamong, said controller comprising: an interface unit coupled to said host system, a buffer memory coupled to said external storage unit, a data transfer control unit coupled to said interface unit and said buffer memory, a bus for interconnecting said interface unit, said buffer memory and said temporary memory to one another, a microprocessor connected to said interface unit, said data transfer control unit and said buffer memory by a second bus, said data transfer control unit including sequencing means for generating first and second enable-signals substantially simultaneously and then generating one of first and second read signals and one of second and first write signals while instructing said temporary memory to fetch data onto said bus, and wherein said sequencing means comprises: a first parameter register storing data from said microprocessor defining transfer direction and transfer-enable information, a first data transfer sequencer connected to said first parameter register and responsive to a data request signal from said interface unit to generate said first enable-signal, said first read signal and said first write signal, said first data transfer sequencer generating instruction signals to said temporary memory to fetch data onto said first bus, a first address counter set by said microprocessor with a data transfer start address for said temporary memory, said first data transfer sequencer updating said first address counter when data is transferred between said first bus and said temporary memory, a second parameter register storing data from said microprocessor defining transfer direction and transfer-enable information, a second data transfer sequencer connected to said second parameter register and responsive to a data request signal from said buffer memory to generate said second enable-signal, said second read signal and said second write signal, said second data transfer sequencer generating instruction signals to said temporary memory to fetch data onto said first bus, and a second address counter set by said microprocessor with a data transfer start address for said temporary memory, said second data transfer sequencer updating said second address counter when data is transferred between said first bus and said temporary memory, said interface unit being supplied with said first enable-signal, said first read signal and said first write signal from said sequencing means for outputting data therein onto said bus in response to said first read signal while receiving said first enable-signal and for fetching data on said bus in response to said first write signal while receiving said first enable-signal, and said buffer memory being supplied with said second enable-signal, said second read signal and said second write signal from said sequencing means for outputting data therein onto said bus in response to said second read signal while receiving said second enable-signal and for fetching data on said bus in response to said second write signal while receiving said second enable-signal.