Patent US5606189A successfully refreshed from Google Patents.
US5606189A
Expired / Lapsed
US
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Dynamic RAM trench capacitor device with contact strap
Assignee: Sharp Corp
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Filing: 1993-08-26
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Granted: 1997-02-25
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Expires: 2013-08-26
Abstract
Abstract A FEC-DRAM of 3 elements/2 bits type having a stack capacitor of increased capacitance to ensure integration with an increased density. The stack capacitor is formed as embedded in a trench, and local wiring is provided to form an electric contact on an element isolation region. When required, the stack capacitor is made to extend onto a word line region. The stack capacitor is given an increased surface area and a greater capacitance, consequently reducing the area occupied and making it possible to provide DRAMs with a higher packing density.
Inventors
- 👤 Alberto O. Adan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/377
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
219 words
A two-transistor, one-capacitor RAM comprising: (a) said two transistors being a pair of capacitively coupled MOS transistors formed side by side on a substrate, the first of said pair of MOS transistors having a source impurity region A embedded in an upper region of the substrate and the second of said pair having a drain impurity region B embedded in said upper region of the substrate, (b) a trench with an insulating layer lining formed in the substrate between impurity regions A and B adjacent to each other at one end of each of the MOS transistors, wherein said trench extends below said upper region of said substrate, and (c) a stack capacitor comprising a first electrode layer connected to and overlaying the impurity region A, a capacitor insulating layer and a second electrode layer connected to the impurity region B through the intermediary of a contact strap, said electrode layers being vertically superimposed, sandwiching said capacitor insulating layer, and embedded in said trench, and being insulated from the substrate by the insulating layer lining in the trench, wherein a first electrode portion of the first electrode layer overlays a portion of the contact strap over impurity region B with an insulating layer therebetween, and the second electrode layer overlays the first electrode portion with an insulating film therebetween.
Claim 2
Dependent Claim
219 words
A two-transistor, one-capacitor RAM comprising: (a) said two transistors being a pair of capacitively coupled MOS transistors formed side by side on a substrate, the first of said pair of MOS transistors having a source impurity region A embedded in an upper region of the substrate and the second of said pair having a drain impurity region B embedded in said upper region of the substrate, (b) a trench with an insulating layer lining formed in the substrate between impurity regions A and B adjacent to each other at one end of each of the MOS transistors, wherein said trench extends below said upper region of said substrate, and (c) a stack capacitor comprising a first electrode layer connected to and overlaying the impurity region A, a capacitor insulating layer and a second electrode layer connected to the impurity region B through the intermediary of a contact strap, said electrode layers being vertically superimposed, sandwiching said capacitor insulating layer, and embedded in said trench, and being insulated from the substrate by the insulating layer lining in the trench, wherein a first electrode portion of the first electrode layer overlays a portion of the contact strap over impurity region B with an insulating layer therebetween, and the second electrode layer overlays the first electrode portion with an insulating film therebetween.
Claim 3
Dependent Claim
31 words
A dynamic RAM as in claim 1 wherein the stack capacitor extends so as to partly cover a word line region serving as the gate of each of the MOS transistors.
Claim 4
Dependent Claim
31 words
A dynamic RAM as in claim 1 wherein said second electrode layer is superimposed over said first electrode layer within said trench and said insulating layer is between the electrode layers.
Claim 5
Dependent Claim
177 words
A dynamic RAM comprising: a first MOS transistor on a substrate having a drain comprising impurity region A and a second MOS transistor on said substrate having a source comprising impurity region B, said impurity regions A and B being adjacent to one another; a trench in said substrate separating said impurity regions A and B, and a stack capacitor capacitively coupling said drain and source of the MOS transistors, said capacitor comprising a first electrode layer conductively coupled to and overlaying said impurity region A, a capacitor insulating film and a floating electrode layer conductively coupled to said impurity region B through the intermediary of a contact strap, said electrode layers being vertically superimposed, sandwiching said capacitor insulating film, and embedded within said trench, and said capacitor insulating film separating said first and second electrodes, wherein a first electrode portion of the first electrode layer overlays a portion of the contact strap over impurity region B with an insulating layer therebetween, and the second electrode layer overlays the first electrode portion with an insulating film therebetween.
Claim 6
Dependent Claim
177 words
A dynamic RAM comprising: a first MOS transistor on a substrate having a drain comprising impurity region A and a second MOS transistor on said substrate having a source comprising impurity region B, said impurity regions A and B being adjacent to one another; a trench in said substrate separating said impurity regions A and B, and a stack capacitor capacitively coupling said drain and source of the MOS transistors, said capacitor comprising a first electrode layer conductively coupled to and overlaying said impurity region A, a capacitor insulating film and a floating electrode layer conductively coupled to said impurity region B through the intermediary of a contact strap, said electrode layers being vertically superimposed, sandwiching said capacitor insulating film, and embedded within said trench, and said capacitor insulating film separating said first and second electrodes, wherein a first electrode portion of the first electrode layer overlays a portion of the contact strap over impurity region B with an insulating layer therebetween, and the second electrode layer overlays the first electrode portion with an insulating film therebetween.
Claim 7
Dependent Claim
143 words
A dynamic random access memory cell for storing two data bits comprising: a first MOS transistor on a substrate having a drain comprising impurity region A and a second MOS transistor on said substrate having a source comprising impurity region B, said impurity regions A and B being adjacent to one another; a trench in said substrate separating said impurity regions A and B, and a floating electrode capacitor capacitively coupling said drain and source of the MOS transistors, said capacitor comprising a first electrode layer conductively coupled to said impurity region A, a capacitor insulating film and a floating electrode layer conductively coupled to said impurity region B through the intermediary of a contact strap, said electrode layers being vertically superimposed, sandwiching said capacitor insulating film and embedded within said trench, and said capacitor insulating film separating said first and second electrodes.
Claim 8
Dependent Claim
143 words
A dynamic random access memory cell for storing two data bits comprising: a first MOS transistor on a substrate having a drain comprising impurity region A and a second MOS transistor on said substrate having a source comprising impurity region B, said impurity regions A and B being adjacent to one another; a trench in said substrate separating said impurity regions A and B, and a floating electrode capacitor capacitively coupling said drain and source of the MOS transistors, said capacitor comprising a first electrode layer conductively coupled to said impurity region A, a capacitor insulating film and a floating electrode layer conductively coupled to said impurity region B through the intermediary of a contact strap, said electrode layers being vertically superimposed, sandwiching said capacitor insulating film and embedded within said trench, and said capacitor insulating film separating said first and second electrodes.
Claim 9
Dependent Claim
147 words
A dynamic RAM comprising: (a) a pair of adjacent transistors, the first of said pair of transistors having a source impurity region A and the second of said pair having a drain impurity region B, (b) a trench with an insulating layer lining formed in the substrate between the pair of transistors and between impurity regions A and B, and (c) a stack capacitor in said trench comprising a first electrode layer operatively connected to and overlaying the impurity region A, a capacitor insulating layer and a second electrode layer operatively connected to the impurity region B, wherein said capacitor capacitively couples the pair of transistors, wherein a first electrode portion of the first electrode layer overlays a portion of the contact strap over impurity region B with an insulating layer therebetween, and the second electrode layer overlays the first electrode portion with an insulating film therebetween.
Claim 10
Dependent Claim
147 words
A dynamic RAM comprising: (a) a pair of adjacent transistors, the first of said pair of transistors having a source impurity region A and the second of said pair having a drain impurity region B, (b) a trench with an insulating layer lining formed in the substrate between the pair of transistors and between impurity regions A and B, and (c) a stack capacitor in said trench comprising a first electrode layer operatively connected to and overlaying the impurity region A, a capacitor insulating layer and a second electrode layer operatively connected to the impurity region B, wherein said capacitor capacitively couples the pair of transistors, wherein a first electrode portion of the first electrode layer overlays a portion of the contact strap over impurity region B with an insulating layer therebetween, and the second electrode layer overlays the first electrode portion with an insulating film therebetween.
References Cited (Backward Citations)
US5012308A
Cited
JPS62131563A
Cited
JPH01218056A
Cited
JPH023274A
Cited
US4958318A
Cited
JPH02297962A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |