Method and apparatus for inserting computer code into a high level language (HLL) software model of an electrical circuit to monitor test coverage of the software model when exposed to test inputs

Claim 1

A method for estimating test coverage of an original high level language description which represents an electrical circuit, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the method comprising the steps of: parsing the original high level language description having at least one executable assignment statement to obtain information of the structure of the electrical circuit represented by the original high level language description; and generating a new high level language description which includes both: (1) new code generated in response to the step of parsing and (2) all the code of the original high level language description necessary for preserving the circuit behavior of the original high level language description; executing the new high level language description via a central processing unit (CPU) in order to simulate the electrical circuit while providing binary test vectors as input to the simulation of the new high level language description; storing, via the new code in the new high level language description, data which indicates whether, during the simulation of the new high level language description of the electrical circuit, the set of variables from the right side of the at least one executable assignment statement has been set to predetermined combinations of values to allow an acceptable level of test coverage of the electrical circuit.

Claim 2

A method for estimating test coverage of an original high level language description which represents an electrical circuit, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the method comprising the steps of: parsing the original high level language description having at least one executable assignment statement to obtain information of the structure of the electrical circuit represented by the original high level language description; and generating a new high level language description which includes both: (1) new code generated in response to the step of parsing and (2) all the code of the original high level language description necessary for preserving the circuit behavior of the original high level language description; executing the new high level language description via a central processing unit (CPU) in order to simulate the electrical circuit while providing binary test vectors as input to the simulation of the new high level language description; storing, via the new code in the new high level language description, data which indicates whether, during the simulation of the new high level language description of the electrical circuit, the set of variables from the right side of the at least one executable assignment statement has been set to predetermined combinations of values to allow an acceptable level of test coverage of the electrical circuit.

Claim 31

A method for determining the test coverage of a plurality of test inputs, the method comprising the steps of: providing an original high level description model of an electrical circuit, the original high level description model having a plurality of assignments statements each of which have a first portion which is subject to assignment from a second portion wherein the second portion contains variables and logical operators; parsing the original high level description model to allow for the generation of new assignments statements using information obtained from the parsing; inserting the new assignments statements into at least a portion of the original high level description model to create a new high level description model; executing in a simulator the new high level description model wherein some of the new assignments statements in the new high level description model create an output file which contains information regarding: (1) whether the first portion of an assignment statements in the plurality of assignments statement has been transitioned to both a true value and a false value; and (2) whether the second portion of each assignments statements in the plurality of assignments statements has been transitioned to all logical combinations in a predetermined set of combinations; and generating a warning/error message file in response to the output file, the warning/error message file identifying possible voids in test coverage of the electrical circuit.

Claim 32

A method for determining the test coverage of a plurality of test inputs, the method comprising the steps of: providing an original high level description model of an electrical circuit, the original high level description model having a plurality of assignments statements each of which have a first portion which is subject to assignment from a second portion wherein the second portion contains variables and logical operators; parsing the original high level description model to allow for the generation of new assignments statements using information obtained from the parsing; inserting the new assignments statements into at least a portion of the original high level description model to create a new high level description model; executing in a simulator the new high level description model wherein some of the new assignments statements in the new high level description model create an output file which contains information regarding: (1) whether the first portion of an assignment statements in the plurality of assignments statement has been transitioned to both a true value and a false value; and (2) whether the second portion of each assignments statements in the plurality of assignments statements has been transitioned to all logical combinations in a predetermined set of combinations; and generating a warning/error message file in response to the output file, the warning/error message file identifying possible voids in test coverage of the electrical circuit.

Claim 37

A method for determining test coverage, the method comprising the steps of: providing a plurality of test vectors where each test vector in the plurality of test vectors contains a plurality of binary values which, when applied to an integrated circuit, test at least a portion of the integrated circuit to ascertain whether the at least a portion of the integrated circuit is operating properly; providing a plurality of simulation instructions wherein the plurality of simulation instructions, when executed, simulate an operation of the integrated circuit, each simulation instruction in the plurality of simulation instructions having an assignment portion and a calculation portion wherein the calculation portion is processed, when executed, to assign a binary value to the assignment portion, the plurality of simulation instructions simulating input terminals of an external portion of the integrated circuit; parsing the plurality of simulation instructions to form parsed information; processing the parsed information to determine which test instructions need to be inserted into the plurality of simulation instructions; inserting the test instructions into the plurality of simulation instructions; executing the plurality of instructions, which includes the test instructions, using the test vectors as input to the simulated input terminals within the plurality of instructions; storing test data while executing via the test instructions; and using the test data to determine the test coverage of the test vectors.

Claim 38

A method for determining test coverage, the method comprising the steps of: providing a plurality of test vectors where each test vector in the plurality of test vectors contains a plurality of binary values which, when applied to an integrated circuit, test at least a portion of the integrated circuit to ascertain whether the at least a portion of the integrated circuit is operating properly; providing a plurality of simulation instructions wherein the plurality of simulation instructions, when executed, simulate an operation of the integrated circuit, each simulation instruction in the plurality of simulation instructions having an assignment portion and a calculation portion wherein the calculation portion is processed, when executed, to assign a binary value to the assignment portion, the plurality of simulation instructions simulating input terminals of an external portion of the integrated circuit; parsing the plurality of simulation instructions to form parsed information; processing the parsed information to determine which test instructions need to be inserted into the plurality of simulation instructions; inserting the test instructions into the plurality of simulation instructions; executing the plurality of instructions, which includes the test instructions, using the test vectors as input to the simulated input terminals within the plurality of instructions; storing test data while executing via the test instructions; and using the test data to determine the test coverage of the test vectors.

Claim 39

A method for determining transitions in an electrical circuit simulation of an electrical circuit, the method comprising the steps of: providing a plurality of test vectors containing a plurality of binary values which are used to test the functionality of the electrical circuit; providing a plurality of instructions which are used to model the operation of the electrical circuit via binary assignment statements which simulate logic gates; parsing the binary assignment statements to obtain assignment information; using the assignment information to insert a set of proper test instructions among the binary assignment statements; executing the binary assignment statements, which include the test instructions, while providing the plurality of test vectors to the binary assignments statements, wherein the test instructions monitor binary switching in the binary assignment statements and record switching data to storage media, the binary switching simulating the electrical circuit; and accessing the storage media to evaluate the switching data to determine an extent of test coverage of the electrical circuit when using the plurality of test vectors.

Claim 40

A method for determining transitions in an electrical circuit simulation of an electrical circuit, the method comprising the steps of: providing a plurality of test vectors containing a plurality of binary values which are used to test the functionality of the electrical circuit; providing a plurality of instructions which are used to model the operation of the electrical circuit via binary assignment statements which simulate logic gates; parsing the binary assignment statements to obtain assignment information; using the assignment information to insert a set of proper test instructions among the binary assignment statements; executing the binary assignment statements, which include the test instructions, while providing the plurality of test vectors to the binary assignments statements, wherein the test instructions monitor binary switching in the binary assignment statements and record switching data to storage media, the binary switching simulating the electrical circuit; and accessing the storage media to evaluate the switching data to determine an extent of test coverage of the electrical circuit when using the plurality of test vectors.

Claim 43

A method for determining whether binary test vectors applied to a software model of an electrical circuit cause a propagation of a single stuck-at fault from an input of a modeled logic gate to an output of the modeled logic gate wherein the software model models the modeled logic gate, the method comprising the steps of: providing the binary test vectors containing a plurality of binary values which are used to test the functionality of the electrical circuit; providing a plurality of instructions which are used to simulate the electrical circuit and the modeled logic gates via binary assignment statements which simulate logic gates; parsing the binary assignment statements to obtain assignment information, the assignment information being used to determine predetermined combinations of gate input values such that all single stuck-at faults on a predetermined gate input of the modeled logic gates will be propagated to a predetermined gate output of the modeled logic gates when the modeled logic gates are simulated with these gate input values; using the assignment information to insert a set of test instructions among the binary assignment statements, the set of test instructions being used to monitor the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate; executing the binary assignment statements, which include the test instructions, while providing the binary test vectors as input, wherein the test instructions monitor the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate; and determining the extent to which binary test vectors applied to the software model of the electrical circuit cause the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate wherein the software model models the modeled logic gate.

Claim 44

A method for determining whether binary test vectors applied to a software model of an electrical circuit cause a propagation of a single stuck-at fault from an input of a modeled logic gate to an output of the modeled logic gate wherein the software model models the modeled logic gate, the method comprising the steps of: providing the binary test vectors containing a plurality of binary values which are used to test the functionality of the electrical circuit; providing a plurality of instructions which are used to simulate the electrical circuit and the modeled logic gates via binary assignment statements which simulate logic gates; parsing the binary assignment statements to obtain assignment information, the assignment information being used to determine predetermined combinations of gate input values such that all single stuck-at faults on a predetermined gate input of the modeled logic gates will be propagated to a predetermined gate output of the modeled logic gates when the modeled logic gates are simulated with these gate input values; using the assignment information to insert a set of test instructions among the binary assignment statements, the set of test instructions being used to monitor the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate; executing the binary assignment statements, which include the test instructions, while providing the binary test vectors as input, wherein the test instructions monitor the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate; and determining the extent to which binary test vectors applied to the software model of the electrical circuit cause the propagation of the single stuck-at fault from the input of the modeled logic gate to the output of the modeled logic gate wherein the software model models the modeled logic gate.