Arrangement of power supply and data input/output pads in semiconductor memory device

Claim 2

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip; a plurality of data input/output buffer means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in said center region, each said data input/output buffer means including a buffer for transmitting and receiving data to and from the corresponding memory block and a pad connected to the buffer; and a plurality of peripheral buffer means arranged in the vicinity of a center portion in said center region along said first direction for receiving an external signal for accessing said plurality of memory blocks, said plurality of data input/output buffer means being arranged in a region excluding the vicinity of said center portion.

Claim 3

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip; a plurality of data input/output buffer means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in said center region, and arranged in groups on one side and on another side with respect to a center portion in said center region along said first direction, each said data input/output buffer means including a buffer for transmitting and receiving a data signal to and from the corresponding memory block and a pad connected to the buffer; and a plurality of power pads arranged adjacent to each respective data input/output buffer means group on each of said one side and said other side for supplying a power source voltage only to an associated data input/output buffer means group.

Claim 4

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip; a plurality of data input/output buffer means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in said center region, and arranged in groups on one side and on another side with respect to a center portion in said center region along said first direction, each said data input/output buffer means including a buffer for transmitting and receiving a data signal to and from the corresponding memory block and a pad connected to the buffer; and a plurality of power pads arranged adjacent to each respective data input/output buffer means group on each of said one side and said other side for supplying a power source voltage only to an associated data input/output buffer means group.

Claim 5

The semiconductor memory device as recited in claim 2, wherein each of said plurality of power pads connects only a power interconnection line for supplying the power source voltage to an associated data input/output buffer means group.

Claim 6

The semiconductor memory device as recited in claim 2, wherein said plurality of data input/output buffer means are aligned on each of said one side and said other side of said center region, and said plurality of power pads are arranged in said center region so as to sandwich a corresponding data input/output buffer means group therebetween on each of said one side and said other side.

Claim 7

The semiconductor memory device as recited in claim 2, further comprising: a peripheral circuit arranged in the center portion between said one side and said other side of said center region, for receiving an external signal controlling an access to said plurality of memory blocks and for controlling the access to said plurality of memory blocks in response to the received external signal; and a peripheral power pad arranged exclusively for said peripheral circuit in said center portion for receiving externally applied power source voltage and supplying the received power source voltage to said peripheral circuit.

Claim 8

The semiconductor memory device as recited in claim 2, wherein each said power pad includes a power supply pad receiving an external power supply voltage for internal transmission, and a ground pad receiving an external ground potential for internal supply.

Claim 9

The semiconductor memory device as recited in claim 2, wherein each said power pad is arranged between data input/output buffer means in each said group of data input/output buffer means.

Claim 10

The semiconductor memory device as recited in claim 2, wherein data input/output buffer means in each said group of data input/output buffer means are arranged on at least two lines in the first direction, and said power pads in each group of data input/output buffer means includes power supply pads supplying a power supply voltage of said power source voltage arranged in alignment with data input/output buffer means on one line of said at least two lines, and ground pads supplying a ground voltage of said power source voltage arranged in alignment with data input/output buffer means on another line of said at least two lines.

Claim 11

The semiconductor memory device as recited in claim 2, wherein data input/output buffer means in each said group of data input/output buffer means are arranged on at least two lines, and said power source voltage comprises one power supply voltage and another power supply voltage and said power pads includes a power supply pad receiving the one power supply voltage for internal transmission and a ground pad receiving the other power supply voltage for internal transmission arranged in each of said at least two lines.

Claim 12

The semiconductor memory device as recited in claim 2, wherein said plurality of power pads include power supply pads supplying one power supply voltage and ground pads supplying another power supply voltage, and said plurality of power pads are aligned with said plurality of data input/output buffer means, and at least one data input/output buffer means is inserted between a power supply pad and a ground pad.

Claim 13

The semiconductor memory device as recited in claim 5, wherein each of said plurality of power pads receives a power supply voltage of a first voltage level, and said peripheral power pad receives a power supply voltage of a second voltage level different from said first voltage level.

Claim 14

The semiconductor memory device as recited in claim 2, wherein said plurality of power pads each connect an interconnection line supplying a power source voltage separate from others.

Claim 15

The semiconductor memory device according to claim 12, further comprising: a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.

Claim 16

The semiconductor memory device as recited in claim 3, wherein said plurality of data input/output buffer means are further grouped into subgroups of a predetermined number of data input/output buffer means in each of said groups, and each of said power pads connects an interconnection line supplying the power source voltage only to an associated subgroup of data input/output buffer means.

Claim 17

The semiconductor memory device according to claim 14, further comprising; a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission thereof to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.

Claim 18

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip; a first pad arranged in a center portion in said center region along said first direction, for supplying a power source voltage to a control circuit for controlling an accessing operation to said plurality of memory blocks; a plurality of second pads arranged in regions opposing to each other with respect to the center portion of said center region, each of said plurality of second pads supplying a power source voltage; and a plurality of data input/output buffers provided corresponding to said plurality of memory blocks, in a region excluding the center portion of said center region, for carrying out input/output of data to a corresponding memory block, said plurality of data input/output buffers each operating with the power source voltage supplied from one of said plurality of second pads provided in a region proximate thereto of said center region.

Claim 19

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip; a first pad arranged in a center portion in said center region along said first direction, for supplying a power source voltage to a control circuit for controlling an accessing operation to said plurality of memory blocks; a plurality of second pads arranged in regions opposing to each other with respect to the center portion of said center region, each of said plurality of second pads supplying a power source voltage; and a plurality of data input/output buffers provided corresponding to said plurality of memory blocks, in a region excluding the center portion of said center region, for carrying out input/output of data to a corresponding memory block, said plurality of data input/output buffers each operating with the power source voltage supplied from one of said plurality of second pads provided in a region proximate thereto of said center region.

Claim 20

The semiconductor memory device as recited in claim 16, wherein said plurality of second pads each connecting only a power source interconnection line supplying the power supply voltage to a data input/output buffer associated therewith.

Claim 21

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in a first direction on both sides of a center region along said first direction on said chip, and divided into first and second groups along said first direction; first and second pads respectively formed in peripheral portions opposing to each other in said center region along said first direction, each of said first and second pads receiving a power source voltage; a third pad arranged in a center portion in said center region along said first direction and receiving the power source voltage; a plurality of data input/output pad portions arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks, each said data input/output pad portions transmitting and receiving data to and from the corresponding memory block, wherein said plurality of data input/output pad portions are divided into first and second groups according to first and second groups of said plurality of memory blocks, a data input/output pad portion provided corresponding to memory blocks in said first group operating in reception of power source voltage from said first pad, and a data input/output pad portion provided corresponding to memory blocks in said second group operating in reception of the power source voltage from said second pad; and peripheral circuitry operating in reception of the power source voltage from said third pad, determining an accessing operation to said plurality of memory blocks in response to an externally applied signal, and controlling the accessing operation according to the determination.

Claim 22

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in a first direction on both sides of a center region along said first direction on said chip, and divided into first and second groups along said first direction; first and second pads respectively formed in peripheral portions opposing to each other in said center region along said first direction, each of said first and second pads receiving a power source voltage; a third pad arranged in a center portion in said center region along said first direction and receiving the power source voltage; a plurality of data input/output pad portions arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks, each said data input/output pad portions transmitting and receiving data to and from the corresponding memory block, wherein said plurality of data input/output pad portions are divided into first and second groups according to first and second groups of said plurality of memory blocks, a data input/output pad portion provided corresponding to memory blocks in said first group operating in reception of power source voltage from said first pad, and a data input/output pad portion provided corresponding to memory blocks in said second group operating in reception of the power source voltage from said second pad; and peripheral circuitry operating in reception of the power source voltage from said third pad, determining an accessing operation to said plurality of memory blocks in response to an externally applied signal, and controlling the accessing operation according to the determination.

Claim 23

The semiconductor memory device as recited in claim 18, wherein said first pad includes a pair of power pads arranged so as to sandwich data input/output pad portions in said first group therebetween along said first direction, and said second pad includes a pair of power pads arranged so as to sandwich data input/output pad portions in said second group therebetween along said first direction.

Claim 24

The semiconductor memory device as recited in claim 19, wherein said pair of power pads in each of said first and second pads includes a power supply pad supplying one power supply voltage of said power source voltage and a ground pad supplying another power supply voltage of said power source voltage.

Claim 25

The semiconductor memory device as recited in claim 19, wherein each said power pad includes a power supply pad supplying one power supply voltage of said power source voltage and a ground pad supplying another power supply voltage of said power source voltage.

Claim 26

The semiconductor memory device as recited in claim 18, wherein said first pad includes a power pad sandwiched between data input/output pad portions in said first group, and said second pad includes a power pad sandwiched between data input/output pad portions in said second group.

Claim 27

A semiconductor memory device, comprising: first and second memory blocks each having a plurality of memory cells; first and second input/output means arranged corresponding to said first and second memory blocks along one side of said first and second memory blocks and spaced from each other along said one side for transmitting and receiving data between a corresponding memory block and an outside of the semiconductor memory device; and peripheral circuitry arranged in a region between said first and second input/output means for controlling an accessing operation to said first and second memory blocks.

Claim 28

A semiconductor memory device, comprising: first and second memory blocks each having a plurality of memory cells; first and second input/output means arranged corresponding to said first and second memory blocks along one side of said first and second memory blocks and spaced from each other along said one side for transmitting and receiving data between a corresponding memory block and an outside of the semiconductor memory device; and peripheral circuitry arranged in a region between said first and second input/output means for controlling an accessing operation to said first and second memory blocks.

Claim 29

The semiconductor memory device as recited in claim 23, wherein said first and second input/output means are arranged in the vicinity of a center portion on said one side of corresponding memory blocks.

Claim 30

The semiconductor memory device as recited in claim 23, further comprising: a first pad formed in a region opposing to a region forming said peripheral circuitry with respect to said first input/output means for receiving an externally applied power source voltage and supplying the received power source voltage to said first input/output means; and a second pad formed in a region opposing to the region forming said peripheral circuitry with respect to said second input/output means for receiving another externally applied power source voltage and supplying the received power source voltage to said second input/output means.

Claim 31

The semiconductor memory device as recited in claim 23, wherein said peripheral circuitry includes a control circuit determining accessing operation, and input means for receiving an externally applied signal and transmitting the received signal to said control circuit.

Claim 32

The semiconductor memory device as recited in claim 23, further comprising a power pad formed in a region between said first and second input/output means for receiving an externally applied power source voltage and transmitting the received power source voltage to said peripheral circuitry as an operation power source voltage.

Claim 33

The semiconductor memory device as recited in claim 23, further comprising: third and fourth memory blocks arranged on said one side of said first and second memory blocks so as to oppose to said first and second memory blocks, respectively, said third and fourth memory blocks each having a plurality of memory cells; third input/output means arranged corresponding to said third memory block and adjacent to said first input/output means for carrying out input/output of data to and from said third memory block with power source voltage supplied from said first pad; and fourth input/output means arranged corresponding to said fourth memory block and adjacent to said second input/output means for carrying out input/output of data to and from said fourth memory block with power source voltage supplied from said second pad, said peripheral circuitry controlling an accessing operation to said first to fourth memory blocks.

Claim 34

The semiconductor memory device as recited in claim 25, wherein only a power source interconnection line for supplying the power source voltage to said first input/output means is connected to said first pad, and only a power source interconnection line for supplying the power source voltage to said second input/output means is connected to said second pad.

Claim 35

The semiconductor memory device as recited in claim 25, wherein said first pad includes a pair of power pads arranged so as to sandwich said first input/output means therebetween in a direction along said one side, and said second pad includes a pair of power pads arranged so as to sandwich said second input/output means therebetween in a direction along said one side.

Claim 36

The semiconductor memory device as recited in claim 28, wherein only a power source interconnection line supplying a power source voltage to both said first and third input/output means is connected to said first pad, and only a power source interconnection line supplying a power source voltage to both said second and fourth input/output means is connected to said second pad.

Claim 37

The semiconductor memory device as recited in claim 28, wherein said first pad includes a pair of power pads arranged so as to sandwich said first and third input/output means therebetween in a direction along said one side, and said second pad includes a pair of power pads arranged so as to sandwich said second and fourth input/output means therebetween in a direction along said one side.

Claim 38

The semiconductor memory device as recited in claim 31, wherein said first pad includes a pair of power pads arranged so as to sandwich said first and third input/output means therebetween in a direction along said one side, and said second pad includes a pair of power pads arranged so as to sandwich said second and fourth input/output means therebetween in a direction along said one side.

Claim 39

A semiconductor memory device, comprising: a first memory block including a plurality of memory cells; a first group of DQ pads receiving and supplying external data for said first memory block, and arranged in alignment with each other; a first group of power pads receiving an external power source voltage for internal transmission, and arranged in alignment with said first group of DQ pads, a second memory block including a plurality of memory cells; a second group of DQ pads receiving and supplying external data for said second memory block, and arranged in alignment with each other; and a second group of power pads arranged in alignment with said second group of DQ pads, and receiving and supplying an external power source voltage for internal transmission.

Claim 40

A semiconductor memory device, comprising: a first memory block including a plurality of memory cells; a first group of DQ pads receiving and supplying external data for said first memory block, and arranged in alignment with each other; a first group of power pads receiving an external power source voltage for internal transmission, and arranged in alignment with said first group of DQ pads, a second memory block including a plurality of memory cells; a second group of DQ pads receiving and supplying external data for said second memory block, and arranged in alignment with each other; and a second group of power pads arranged in alignment with said second group of DQ pads, and receiving and supplying an external power source voltage for internal transmission.

Claim 41

The semiconductor memory device as recited in claim 34, wherein said external source voltage comprises a power supply voltage and a ground voltage, and wherein said first group of power pads includes a power supply pad supplying the power supply voltage and a ground pad which are arranged sandwiching at least one DQ pad of said first group of DQ pads, and said second group of power pads includes a power supply pad supplying the power supply voltage, and a ground pad supplying the ground potential which are arranged sandwiching at least one DQ pad in said second group of DQ pads.

Claim 42

The semiconductor memory device as recited in claim 34, wherein said external source voltage comprises a power supply voltage and a ground voltage, and wherein said first group of power pads consists of power supply pads supplying the power supply voltage, and said second group of power pads consists of ground pads supplying the ground voltage, and said first group of power pads and said second group of power pads are arranged on two lines in a region between said first and second memory blocks.

Claim 43

The semiconductor memory device as recited in claim 35, wherein said first group of power pads and said first group of DQ pads are arranged on an outer side of said first memory block opposing to an inner region between said first and second memory blocks, and said second group of DQ pads and said second group of power pads are arranged on an outer side of said second memory block opposing to said inner region.

Claim 44

The semiconductor memory device as recited in claim 35, wherein said first and second groups of DQ pads and said first and second groups of power pads are arranged in a region between said first and second memory blocks.

Claim 45

The semiconductor memory device as recited in claim 34, wherein said external source voltage includes a power supply voltage and a ground voltage, and wherein said first group of power pads includes power supply pads each supplying the power supply voltage and ground pads each supplying the ground voltage, which are arranged alternately on a line, and said second group of power pads includes power supply pads each supplying the power supply voltage and ground pads each supplying the ground voltage, which are alternately arranged on another line.

Claim 46

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks each including a plurality of memory cells; a plurality of DQ buffers provided corresponding to said plurality of memory blocks for transmitting and receiving data to and from corresponding memory blocks; a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission thereof and provided extending over said chip and at least one of said plurality of memory blocks; a plurality of power pads provided corresponding to each respective memory block and coupled to said power bus for supplying the voltage received from the power bus to said plurality of DQ buffers provided corresponding to corresponding memory blocks.

Claim 47

A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks each including a plurality of memory cells; a plurality of DQ buffers provided corresponding to said plurality of memory blocks for transmitting and receiving data to and from corresponding memory blocks; a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission thereof and provided extending over said chip and at least one of said plurality of memory blocks; a plurality of power pads provided corresponding to each respective memory block and coupled to said power bus for supplying the voltage received from the power bus to said plurality of DQ buffers provided corresponding to corresponding memory blocks.

Claim 48

The semiconductor memory device as recited in claim 40, wherein said plurality of power pads each connect an interconnection line supplying a power source voltage separate from others.

Claim 49

The semiconductor memory device as recited in claim 40, wherein said plurality of DQ buffers are grouped into groups, one group for each memory block, and each group include a second plurality of DQ buffers, and said second plurality of DQ buffers are grouped into subgroups of a predetermined number of DQ buffers in each of said groups, and each of said power pads connects an interconnection line supplying the power source voltage only to an associated subgroup of DQ buffers.

Claim 50

A semiconductor memory device, comprising: a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns; a plurality of data buses provided corresponding to each of said plurality of memory blocks, each of said plurality of data buses arranged extending along only a corresponding memory block; and a plurality of data input/output pad portions for communicating data with the memory blocks through the data buses, a predetermined number of the data input/output pad portions being provided for each of the memory blocks, and each of the data input/output pad portions communicating data with only a corresponding memory block.

Claim 51

A semiconductor memory device, comprising: a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns; a plurality of data buses provided corresponding to each of said plurality of memory blocks, each of said plurality of data buses arranged extending along only a corresponding memory block; and a plurality of data input/output pad portions for communicating data with the memory blocks through the data buses, a predetermined number of the data input/output pad portions being provided for each of the memory blocks, and each of the data input/output pad portions communicating data with only a corresponding memory block.

Claim 52

The semiconductor memory device according to claim 43, wherein said plurality of memory blocks are arranged on both sides of a center region extending in a first direction, and said plurality of data input/output pad portions are arranged alignedly on said center region.

Claim 53

The semiconductor memory device according to claim 43, wherein said plurality of memory blocks are arranged on both sides of a center line, and each of said plurality of data input/output pad portions are arranged on an outer side opposing to the center line of a corresponding memory block.

Claim 54

The semiconductor memory device according to claim 43, wherein each of said plurality of memory blocks has a predetermined number of memory cells selected at a time, and wherein said semiconductor memory device further comprises a compressor means provided for each of said plurality of memory blocks and coupled to receive data of the predetermined number of memory cells of a corresponding memory block for compressing the data of the predetermined number of memory cells when enabled in response to a test mode instruction signal.

Claim 55

The semiconductor memory device according to claim 46, wherein said plurality of memory blocks are provided on both sides of a center region extending in a first direction, and wherein said semiconductor memory device further comprises a further compressor means provided commonly for each set of memory blocks facing to each other with respect to said center region and further compressing data compressed by and received from the compressor means provided for a corresponding set of memory blocks when enabled in response to said test mode instruction signal.

Claim 56

The semiconductor memory device according to claim 46, wherein said compressor means supplies the compressed data to a data input/output pad portion provided for a corresponding memory block.

Claim 57

The semiconductor memory device according to claim 46, wherein said compressor means comprises a coincidence detector for detecting whether data received from the predetermined number of memory cells are identical in logic with each other.

Claim 58

The semiconductor memory device according to claim 47, wherein said further compressor means supplies the compressed data to an input/output pad portion provided for a corresponding set of memory blocks.