Stacked capacitor type semiconductor memory device with good flatness characteristics

Claim 2

A dynamic random access memory device comprising: a semiconductor substrate; a first insulating layer formed on a memory cell array area and a peripheral circuit area of said semiconductor substrate having a plurality of holes leading to a plurality of impurity doped regions, respectively; a plurality of contacting means, each formed in one of said plurality of holes; a second insulating layer formed on said first insulating layer and having a plurality of openings in said memory cell array area; and a plurality of stacked capacitors each buried in one of said openings, each of said stacked capacitors being electrically connected via one of said plurality of contacting means to one of said plurality of impurity doped regions of said semiconductor substrate.

Claim 3

A dynamic random access memory device comprising: a semiconductor substrate; a first insulating layer formed on a memory cell array area and a peripheral circuit area of said semiconductor substrate; a second insulating layer formed on said first insulating layer and having a groove in said memory cell array area to divide said second insulating layer in said memory cell array area into a plurality of islands; a plurality of stacked capacitors each formed on one of said islands, said stacked capacitors being electrically connected, via contacting means formed in contact holes of said islands and contact holes of said first insulating layer, to impurity doped regions of said semiconductor substrate.

Claim 4

A dynamic random access memory device comprising: a semiconductor substrate; a first insulating layer formed on a memory cell array area and a peripheral circuit area of said semiconductor substrate; a second insulating layer formed on said first insulating layer and having a groove in said memory cell array area to divide said second insulating layer in said memory cell array area into a plurality of islands; a plurality of stacked capacitors each formed on one of said islands, said stacked capacitors being electrically connected, via contacting means formed in contact holes of said islands and contact holes of said first insulating layer, to impurity doped regions of said semiconductor substrate.

Claim 5

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; an impurity doped region formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a first contact hole leading to said impurity doped region; a contacting means formed in said first contact hole; a second insulating layer formed on said first insulating layer and having an opening leading to said first insulating layer; a capacitor lower electrode layer, formed within said opening and being electrically connected via said contacting means to said impurity region; a first capacitor insulating layer formed on said capacitor lower electrode layer; and a first capacitor upper electrode layer formed on said first capacitor insulating layer.

Claim 6

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; an impurity doped region formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a first contact hole leading to said impurity doped region; a contacting means formed in said first contact hole; a second insulating layer formed on said first insulating layer and having an opening leading to said first insulating layer; a capacitor lower electrode layer, formed within said opening and being electrically connected via said contacting means to said impurity region; a first capacitor insulating layer formed on said capacitor lower electrode layer; and a first capacitor upper electrode layer formed on said first capacitor insulating layer.

Claim 7

A device as set forth in claim 3, further comprising: a second capacitor upper electrode layer formed on a sidewall within said opening of said second insulating layer; and a second capacitor insulating layer formed between said second capacitor upper electrode layer and said capacitor lower electrode, said second capacitor upper electrode layer being electrically connected to said first capacitor upper electrode layer.

Claim 8

A device as set forth in claim 4, further comprising: a third capacitor upper electrode layer formed on said second insulating layer; and a third capacitor insulating layer formed between said first capacitor upper electrode layer and said third capacitor upper electrode layer, said third capacitor upper electrode layer being connected via a contact hole of said third capacitor insulating layer to said first capacitor upper electrode layer.

Claim 9

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; an impurity doped region formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a first contact hole leading to said impurity doped region; a second insulating layer formed on said first insulating layer and having a plurality of grooves to form an insulating island having a second contact hole leading to said first contact hole; a capacitor lower electrode layer formed on and surrounding said insulating island and being electrically connected via a contacting means formed in said first and second contact holes to said impurity region; a first capacitor insulating layer formed on said capacitor lower electrode layer; and a first capacitor upper electrode layer formed on said first capacitor insulating layer.

Claim 10

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; an impurity doped region formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a first contact hole leading to said impurity doped region; a second insulating layer formed on said first insulating layer and having a plurality of grooves to form an insulating island having a second contact hole leading to said first contact hole; a capacitor lower electrode layer formed on and surrounding said insulating island and being electrically connected via a contacting means formed in said first and second contact holes to said impurity region; a first capacitor insulating layer formed on said capacitor lower electrode layer; and a first capacitor upper electrode layer formed on said first capacitor insulating layer.

Claim 11

A device as set forth in claim 6, further comprising a second capacitor upper electrode layer formed on said first insulating layer and electrically connected to said first capacitor upper electrode layer; and a second insulating layer formed on said second capacitor upper electrode so as to insulate said second capacitor upper electrode from said capacitor lower electrode.

Claim 12

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; a plurality of impurity doped regions formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a plurality of contact holes each leading to one of said impurity doped regions; a second insulating layer formed on said first insulating layer and having a plurality of openings each corresponding to one of said contact holes; a plurality of contacting means, each formed in one of said plurality of contact holes; a plurality of capacitor electrode layers, each formed on a bottom of one of said openings and along a sidewall thereof and being electrically connected via one of said plurality of contacting means to one of said impurity doped regions; a capacitor insulating layer formed on said capacitor electrode layers; and a counter capacitor electrode layer formed on said capacitor insulating layer.

Claim 13

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; a plurality of impurity doped regions formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a plurality of contact holes each leading to one of said impurity doped regions; a second insulating layer formed on said first insulating layer and having a plurality of openings each corresponding to one of said contact holes; a plurality of contacting means, each formed in one of said plurality of contact holes; a plurality of capacitor electrode layers, each formed on a bottom of one of said openings and along a sidewall thereof and being electrically connected via one of said plurality of contacting means to one of said impurity doped regions; a capacitor insulating layer formed on said capacitor electrode layers; and a counter capacitor electrode layer formed on said capacitor insulating layer.

Claim 14

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; a plurality of impurity doped regions formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a plurality of first contact holes each leading to one of said impurity doped regions; a second insulating layer formed on said first insulating layer and having a plurality of openings each corresponding to one of said first contact holes; a plurality of contact means, each formed in one of said plurality of contact holes; a plurality of capacitor electrode layers, each formed on a bottom of one of said openings and extending along a side wall thereof, and being electrically connected via one of said contacting means to one of said impurity doped regions; a first capacitor insulating layer formed on a surface of said capacitor electrode layers; a first counter capacitor electrode layer formed on said first capacitor insulating layer; a plurality of second counter capacitor electrode layers each formed on a sidewall of one of said openings; and a plurality of second insulating layers each formed between said first counter capacitor electrode layer and one of said second counter capacitor electrode layers, said second counter capacitor electrode layers being electrically connected via second contact holes of said second capacitor insulating layer to said first counter capacitor electrode layer.

Claim 15

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; a plurality of impurity doped regions formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a plurality of first contact holes each leading to one of said impurity doped regions; a second insulating layer formed on said first insulating layer and having a plurality of openings each corresponding to one of said first contact holes; a plurality of contact means, each formed in one of said plurality of contact holes; a plurality of capacitor electrode layers, each formed on a bottom of one of said openings and extending along a side wall thereof, and being electrically connected via one of said contacting means to one of said impurity doped regions; a first capacitor insulating layer formed on a surface of said capacitor electrode layers; a first counter capacitor electrode layer formed on said first capacitor insulating layer; a plurality of second counter capacitor electrode layers each formed on a sidewall of one of said openings; and a plurality of second insulating layers each formed between said first counter capacitor electrode layer and one of said second counter capacitor electrode layers, said second counter capacitor electrode layers being electrically connected via second contact holes of said second capacitor insulating layer to said first counter capacitor electrode layer.

Claim 16

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; a plurality of impurity doped regions formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a plurality of first contact holes each leading to one of said impurity doped regions; a plurality of insulating islands, each having a second contact hole leading to one of said first contact hole; a plurality of capacitor electrode layers, each formed on a top surface of one of said insulating islands and at least sidewalls thereof and being electrically connected, via a connecting means formed in a respective one of said second contact holes and a respective one of said first contact holes, to one of said impurity doped regions; a first capacitor insulating layer formed on said capacitor electrode layers; and a first counter capacitor electrode layer formed on said first capacitor insulating layer.

Claim 17

A stacked capacitor type semiconductor memory device comprising: a semiconductor substrate; a plurality of impurity doped regions formed within said semiconductor substrate; a first insulating layer formed on said semiconductor substrate and having a plurality of first contact holes each leading to one of said impurity doped regions; a plurality of insulating islands, each having a second contact hole leading to one of said first contact hole; a plurality of capacitor electrode layers, each formed on a top surface of one of said insulating islands and at least sidewalls thereof and being electrically connected, via a connecting means formed in a respective one of said second contact holes and a respective one of said first contact holes, to one of said impurity doped regions; a first capacitor insulating layer formed on said capacitor electrode layers; and a first counter capacitor electrode layer formed on said first capacitor insulating layer.

Claim 18

A device as set forth in claim 10, further comprising: a second counter capacitor electrode layer formed on said first insulating layer and surrounding said insulating islands, said second counter capacitor electrode layer being electrically connected to said first counter capacitor electrode layer; and a second capacitor insulating layer formed between said second counter capacitor electrode layer and said plurality of capacitor electrode layers.

Claim 19

A device as set forth in claim 1, whereby said second insulator is made thick and said stacked capacitors are buried in said second insulator layer to minimize a vertical step, said step being a relative difference in device thickness of said peripheral circuit area and said memory cell array area, thereby improving integration of said random access device.

Claim 20

A device as set forth in claim 12, wherein said second insulator has a thickness between 500 and 1000 nm.

Claim 21

A device as set forth in claim 12 wherein said first insulator comprises two separate layers of insulating material formed one on top of the other over said memory cell array area and said peripheral circuit area.

Claim 22

A device as set forth in claim 2, whereby said second insulator is made thick and said stacked capacitors are formed on said islands of said second insulating layer to minimize a vertical step, said step being a relative difference in device thickness of said peripheral circuit area and said memory cell array area, thereby improving integration of said random access device.

Claim 23

A device as set forth in claim 15, wherein said second insulator has a thickness between 500 and 1000 nm.

Claim 24

A device as set forth in claim 15 wherein said first insulator comprises two separate layers of insulating material formed one on top of the other over said memory cell array area and said peripheral circuit area.

Claim 25

A dynamic random access memory device comprising: a semiconductor substrate; a first insulating layer formed on a memory cell array area and a peripheral circuit area of said semiconductor substrate; a plurality of stacked capacitors formed on the memory cell array area; a means for making planar an area between said memory cell array area and said peripheral circuit area of said semiconductor substrate, thereby reducing a vertical step between said memory cell array area and said peripheral circuit area and improving integration of said random access device.

Claim 26

A dynamic random access memory device comprising: a semiconductor substrate; a first insulating layer formed on a memory cell array area and a peripheral circuit area of said semiconductor substrate; a plurality of stacked capacitors formed on the memory cell array area; a means for making planar an area between said memory cell array area and said peripheral circuit area of said semiconductor substrate, thereby reducing a vertical step between said memory cell array area and said peripheral circuit area and improving integration of said random access device.

Claim 27

A device as set forth in claim 18, wherein said means for making planar comprises a thick insulator from 500 to 1000 nm to contain said stacked capacitor and compensate, in said peripheral circuit area, for a height of said stacked capacitor in said memory cell array area.