Patent US5604156A successfully refreshed from Google Patents.
US5604156A
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US
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Wire forming method for semiconductor device
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-11-20
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Granted: 1997-02-18
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Expires: 2015-11-20
Abstract
Abstract A wire forming method for a semiconductor device includes the steps of depositing an insulation material on a semiconductor substrate and patterning the insulation material to form a first insulation layer, forming a lower capping layer on the first insulation layer, etching the lower capping layer and the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate, forming a wire layer over the capping layer and the first part of the semiconductor substrate, performing a chemical and mechanical polishing (CMP) process with respect to the wire layer and the lower capping layer to expose the first insulation layer, forming a second insulation layer over the wire layer and the first insulation layer, and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate. The wire forming method can prevent the lifting of the wire layer, the splitting of the lower insulation layer, and the formation of a protrusion n the second contact hole.
Inventors
- 👤 U-In Chung
- 👤 Jae-duk Kim
- 👤 Chang-ki Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/076; H10P; H10P14/00; H10P14/60; H10P14/65; H10P14/6516; H10P14/6548; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6923; H10P14/6928; H10P14/6936; H10P14/6938; H10P14/6939; H10P14/69391; H10P14/694; H10P14/6943; H10P14/69433; H10P95/00; H10P95/06; H10P95/062; H10W20/031; H10W20/032; H10W20/033; H10W20/056; H10W20/081; H10W20/084; H10W20/092; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
176 words
A wire forming method for a semiconductor device including the steps of: forming a first insulation layer on a semiconductor substrate; forming recessed portions on the surface of the first insulation layer by etching the first insulation layer to a preferred thickness; forming a lower capping layer over the first insulation layer after the step of forming recessed portions; etching the lower capping layer and one of the recessed portions of the first insulation layer to form a first contact hole exposing a first portion of the semiconductor substrate; forming a barrier layer over the lower capping layer and the first part of the semiconductor substrate; forming a wire layer over the barrier layer; performing a chemical and mechanical polishing (CMP) process on the wire layer, the barrier layer, and the lower capping layer to expose the first insulation layer; forming a second insulation layer over the wire layer and the first insulation layer; and etching the first and second insulation layers to form a second contact hole that exposes a second part of the substrate.
Claim 2
Dependent Claim
176 words
A wire forming method for a semiconductor device including the steps of: forming a first insulation layer on a semiconductor substrate; forming recessed portions on the surface of the first insulation layer by etching the first insulation layer to a preferred thickness; forming a lower capping layer over the first insulation layer after the step of forming recessed portions; etching the lower capping layer and one of the recessed portions of the first insulation layer to form a first contact hole exposing a first portion of the semiconductor substrate; forming a barrier layer over the lower capping layer and the first part of the semiconductor substrate; forming a wire layer over the barrier layer; performing a chemical and mechanical polishing (CMP) process on the wire layer, the barrier layer, and the lower capping layer to expose the first insulation layer; forming a second insulation layer over the wire layer and the first insulation layer; and etching the first and second insulation layers to form a second contact hole that exposes a second part of the substrate.
Claim 3
Dependent Claim
25 words
A wire forming method for a semiconductor device as claimed in claim 1, wherein the wire layer is formed of a refractory metal or copper.
Claim 4
Dependent Claim
32 words
A wire forming method for a semiconductor device as claimed in claim 2, wherein the refractory metal is selected from the group consisting of tungsten (W), molybdenum (Mo), and titanium nitride (TIN).
Claim 5
Dependent Claim
27 words
A wire forming method for a semiconductor device as claimed in claim 1, wherein the first and second insulation layers are formed of a ductile insulation material.
Claim 6
Dependent Claim
34 words
A wire forming method for a semiconductor device as claimed in claim 4, wherein the ductile insulation material is selected from the group consisting of BPSG, BSG, PSG, GeSiO 2 , GeBPSG and AsBPSG.
Claim 7
Dependent Claim
25 words
A wire forming method for a semiconductor device as claimed in claim 1, wherein the lower capping layer is formed of a nonductile insulation material.
Claim 8
Dependent Claim
42 words
A wire forming method for a semiconductor device as claimed in claim 5, wherein the non-ductile insulation material is selected from the group consisting of SiN, SiO 2 , Si 3 N 4 , BN, SiBN and Al 2 O 3 .
Claim 9
Dependent Claim
203 words
A wire forming method for a semiconductor device including the steps of: forming a first insulation layer on a semiconductor substrate; forming recessed portions on the surface of the first insulation layer by etching the first insulation layer to a preferred thickness; forming a lower capping layer over the first insulation layer after the step of forming recessed portions; etching the lower capping layer and one of the recessed portions of the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate; forming a barrier layer over the lower capping layer and the first part of the semiconductor substrate; forming a wire layer over the barrier layer; performing a primary chemical and mechanical polishing (CMP) step with respect to the wire layer and the barrier layer to expose the lower capping layer; performing a secondary chemical and mechanical polishing (CMP) step with respect to the lower capping layer and the wire layer to expose the first insulation layer; forming a second insulation layer over the wire layer and the first insulation layer; and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate.
Claim 10
Dependent Claim
203 words
A wire forming method for a semiconductor device including the steps of: forming a first insulation layer on a semiconductor substrate; forming recessed portions on the surface of the first insulation layer by etching the first insulation layer to a preferred thickness; forming a lower capping layer over the first insulation layer after the step of forming recessed portions; etching the lower capping layer and one of the recessed portions of the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate; forming a barrier layer over the lower capping layer and the first part of the semiconductor substrate; forming a wire layer over the barrier layer; performing a primary chemical and mechanical polishing (CMP) step with respect to the wire layer and the barrier layer to expose the lower capping layer; performing a secondary chemical and mechanical polishing (CMP) step with respect to the lower capping layer and the wire layer to expose the first insulation layer; forming a second insulation layer over the wire layer and the first insulation layer; and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate.
Claim 11
Dependent Claim
25 words
A wire forming method for a semiconductor device as claimed in claim 8, wherein the wire layer is formed of a refractory metal or copper.
Claim 12
Dependent Claim
32 words
A wire forming method for a semiconductor device as claimed in claim 9, wherein the refractory metal is selected from the group consisting of tungsten (W), molybdenum (Mo), and titanium nitride (TIN).
Claim 13
Dependent Claim
27 words
A wire forming method for a semiconductor device as claimed in claim 8, wherein the first and second insulation layers are formed of a ductile insulation material.
Claim 14
Dependent Claim
34 words
A wire forming method for a semiconductor device as claimed in claim 11, wherein the ductile insulation material is selected from the group consisting of BPSG, BSG, PSG, GeSiO 2 , GeBPSG and AsBPSG.
Claim 15
Dependent Claim
25 words
A wire forming method for a semiconductor device as claimed in claim 8, wherein the lower capping layer is formed of a nonductile insulation material.
Claim 16
Dependent Claim
42 words
A wire forming method for a semiconductor device as claimed in claim 13, wherein the nonductile insulation material is selected from the group consisting of SiN, SiO 2 , Si 3 N 4 , BN, SiBN and Al 2 O 3 .
Claim 17
Dependent Claim
249 words
A wire forming method for a semiconductor device including the steps of: forming a first insulation layer on a semiconductor substrate; forming recessed portions on the surface of the first insulation layer by etching the first insulation layer to a preferred thickness; forming a lower capping layer over the first insulation layer after the step of forming recessed portions; etching the lower capping layer and one of the recessed portions of the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate; forming a barrier layer over the lower capping layer and the first part of the semiconductor substrate; forming a wire layer over the barrier layer; performing a primary chemical and mechanical polishing (CMP) step with respect to the wire layer, the barrier layer, and the lower capping layer to expose the first insulation layer; selectively etching the wire layer and the barrier layer to form a step difference between the wire layer and the first insulation layer; forming an upper capping layer over the wire layer and the first insulating layer; performing a secondary chemical and mechanical polishing (CMP) step with respect to the upper capping layer, the first insulation layer, and the lower capping layer to remove the step difference; forming a second insulation layer over the upper capping layer and the first insulation layer; and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate.
Claim 18
Dependent Claim
249 words
A wire forming method for a semiconductor device including the steps of: forming a first insulation layer on a semiconductor substrate; forming recessed portions on the surface of the first insulation layer by etching the first insulation layer to a preferred thickness; forming a lower capping layer over the first insulation layer after the step of forming recessed portions; etching the lower capping layer and one of the recessed portions of the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate; forming a barrier layer over the lower capping layer and the first part of the semiconductor substrate; forming a wire layer over the barrier layer; performing a primary chemical and mechanical polishing (CMP) step with respect to the wire layer, the barrier layer, and the lower capping layer to expose the first insulation layer; selectively etching the wire layer and the barrier layer to form a step difference between the wire layer and the first insulation layer; forming an upper capping layer over the wire layer and the first insulating layer; performing a secondary chemical and mechanical polishing (CMP) step with respect to the upper capping layer, the first insulation layer, and the lower capping layer to remove the step difference; forming a second insulation layer over the upper capping layer and the first insulation layer; and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate.
Claim 19
Dependent Claim
25 words
A wire forming method for a semiconductor device as claimed in claim 15, wherein the upper capping layer is formed of a nonductile insulation material.
Claim 20
Dependent Claim
25 words
A wire forming method for a semiconductor device as claimed in claim 15, wherein the wire layer is formed of a refractory metal or copper.
Claim 21
Dependent Claim
32 words
A wire forming method for a semiconductor device as claimed in claim 17, wherein the refractory metal is selected from the group consisting of tungsten (W), molybdenum (Mo), and titanium nitride (TIN).
Claim 22
Dependent Claim
27 words
A wire forming method for a semiconductor device as claimed in claim 15, wherein the first and second insulation layers are formed of a ductile insulation material.
Claim 23
Dependent Claim
34 words
A wire forming method for a semiconductor device as claimed in claim 19, wherein the ductile insulation material is selected from the group consisting of BPSG, BSG, PSG, GeSiO 2 , GeBPSG and AsBPSG.
Claim 24
Dependent Claim
25 words
A wire forming method for a semiconductor device as claimed in claim 15, wherein the lower capping layer is formed of a nonductile insulation material.
Claim 25
Dependent Claim
42 words
A wire forming method for a semiconductor device as claimed in claim 21, wherein the non-ductile insulation material is selected from the group consisting of SiN, SiO 2 , Si 3 N 4 , BN, SiBN and Al 2 O 3 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-18 | 2000-08-19 | 2001-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-18 | 2004-08-19 | 2005-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-18 | 2008-08-19 | 2009-02-18 | $7700.00 | Window Closed / Lapsed |