US5602989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus connectivity verification technique
Assignee: Advanced Micro Devices Inc
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Filing: 1995-05-15
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Granted: 1997-02-11
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Expires: 2015-05-15
Abstract
Abstract A testing method and apparatus for improving an efficiency of a post-production connectivity test of a bus coupling a semiconductor device to a bus connector each integrated on a system board. The method includes applying a special test fixture to the connector in lieu of a device designed to be operated by the particular bus. The test fixtures includes a plurality of memories having inputs and outputs connected to one of the conductors of the bus. By applying known patterns of signals to the memories and reading the outputs of the memories, connectivity of the bus is tested without operating the bus.
Inventors
- 👤 Percy R. Aria
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:59
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G01; G01R; G01R31/00; G01R31/50; G01R31/58; G01R31/66; G01R31/70
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
141 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state.
Claim 2
Independent Claim
141 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state.
Claim 3
Independent Claim
247 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein said memory is responsive to a second signal at said input for setting a second predetermined state at said output, said second predetermined state different than said first predetermined state, the method further comprising the steps of: asserting said second signal, after said accessing step, to said input using said first set of conductors; and thereafter accessing a second output state of said memory using said second set of conductors; and thereafter comparing said second output state to said second predetermined state, wherein said first and said second set of conductors are not improperly connected when said second output state matches said second predetermined state.
Claim 4
Independent Claim
247 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein said memory is responsive to a second signal at said input for setting a second predetermined state at said output, said second predetermined state different than said first predetermined state, the method further comprising the steps of: asserting said second signal, after said accessing step, to said input using said first set of conductors; and thereafter accessing a second output state of said memory using said second set of conductors; and thereafter comparing said second output state to said second predetermined state, wherein said first and said second set of conductors are not improperly connected when said second output state matches said second predetermined state.
Claim 5
Independent Claim
192 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein said memory is a D-type flip-flop and said first set of conductors include a first connection to a data input of said flip-flop and a second connection to a clock input of said flip-flop, and said second set of conductors include a third connection to an output of said flip-flop.
Claim 6
Independent Claim
192 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein said memory is a D-type flip-flop and said first set of conductors include a first connection to a data input of said flip-flop and a second connection to a clock input of said flip-flop, and said second set of conductors include a third connection to an output of said flip-flop.
Claim 7
Independent Claim
209 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein said memory is a counter having an input and an output wherein a count value stored in said counter and provided at said output is responsive to a particular signal at said input, and said first set of conductors include a connection to said counter input and said second set of conductors include connections to said counter output to access said count value as said predetermined value.
Claim 8
Independent Claim
209 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein said memory is a counter having an input and an output wherein a count value stored in said counter and provided at said output is responsive to a particular signal at said input, and said first set of conductors include a connection to said counter input and said second set of conductors include connections to said counter output to access said count value as said predetermined value.
Claim 9
Independent Claim
210 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein the bus includes N number of conductors, N being a whole number at least equal to two, and wherein said test fixture includes a plurality of memories each having a set of conductors coupled to an input and a set of conductors coupled to an output wherein each of said N number of conductors is in one of said sets of conductors coupled to one of said memories.
Claim 10
Independent Claim
210 words
A method for testing a connectivity of a bus between a semiconductor device affixed to a wiring board and a connector coupled to the wiring board, comprising the steps of: attaching a test fixture to the connector, said test fixture including a memory responsive to an assertion of a first signal at an input of said memory to set a predetermined state at an output of said memory; thereafter asserting said first signal to said memory using a first set of conductors of the bus coupled to said input; thereafter accessing an output state of said memory using a second set of conductors of the bus coupled to said output; and thereafter comparing said output state to said predetermined state, wherein said first and said second sets of conductors are not improperly connected when said output state matches said predetermined state; wherein the bus includes N number of conductors, N being a whole number at least equal to two, and wherein said test fixture includes a plurality of memories each having a set of conductors coupled to an input and a set of conductors coupled to an output wherein each of said N number of conductors is in one of said sets of conductors coupled to one of said memories.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |