Digital phase locked loop

Claim 2

A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter, comprising: a) a digital input circuit receiving said at least one input signal; b) a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal; c) a stable local oscillator for providing clock signals to said digital controlled oscillator; d) tapped delay line means for receiving the output signal of said digital controlled oscillator, said tapped delay line means comprising a plurality of buffers each introducing a delay of less than one clock cycle of said digital controlled oscillator, said tapped delay line means producing an output signal from a tap determined by said control signal; e) a digital phase comparator for receiving said at least one input signal from said input circuit and said output signal from said tapped delay line means to generate a digital input signal controlling said digital controlled oscillator; and wherein said digital controlled oscillator is an adding type rate multiplier that generates said output signal when attaining an overflow condition, the remainder term upon attainment of said overflow condition generating said control signal.

Claim 3

A digital phase locked loop as claimed in claim 1, wherein said tapped delay line means comprises a pair of tapped lines to permit the generation of a frequency at twice the output frequency of the digital controlled oscillator.

Claim 4

A digital phase locked loop as claimed in claim 1, wherein said oscillator is coded according to a mixed coding scheme.

Claim 5

A digital phase locked loop as claimed in claim 1, wherein the most significant portion of the digital input signal is binary coded and the least significant part is BCD coded.

Claim 6

A digital phase locked loop as claimed in claim 1, wherein said digital input circuit and said phase comparator are clocked by signals regenerated from said phase locked loop.

Claim 7

A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter, comprising: a) a digital input circuit receiving said at least one input signal; b) a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal; c) a stable local oscillator for providing clock signals to said digital controlled oscillator; d) tapped delay line means for receiving the output signal of said digital controlled oscillator, said tapped delay line means comprising a plurality of buffers each introducing a delay of less than one clock cycle of said digital controlled oscillator, said tapped delay line means producing an output signal from a tap determined by said control signal; e) a digital phase comparator for receiving said at least one input signal from said input circuit and said output signal from said tapped delay line means to generate a digital input signal controlling said digital controlled oscillator; and wherein said digital input circuit has two inputs for receiving respective first and second input signals, either one of said input signals being capable of serving as a reference signal for said digital controlled oscillator, means for continually monitoring the phase shift between said first and second input signals, and means for generating upon changeover from one input signal to the other a virtual reference signal from said other input signal that is phase shifted thereto by an amount substantially equal to said phase shift between said first and second input signals so as to minimize phase jump on changeover between input signals.

Claim 8

A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter, comprising: a) a digital input circuit receiving said at least one input signal; b) a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal; c) a stable local oscillator for providing clock signals to said digital controlled oscillator; d) tapped delay line means for receiving the output signal of said digital controlled oscillator, said tapped delay line means comprising a plurality of buffers each introducing a delay of less than one clock cycle of said digital controlled oscillator, said tapped delay line means producing an output signal from a tap determined by said control signal; e) a digital phase comparator for receiving said at least one input signal from said input circuit and said output signal from said tapped delay line means to generate a digital input signal controlling said digital controlled oscillator; and wherein said digital input circuit has two inputs for receiving respective first and second input signals, either one of said input signals being capable of serving as a reference signal for said digital controlled oscillator, means for continually monitoring the phase shift between said first and second input signals, and means for generating upon changeover from one input signal to the other a virtual reference signal from said other input signal that is phase shifted thereto by an amount substantially equal to said phase shift between said first and second input signals so as to minimize phase jump on changeover between input signals.

Claim 9

A digital phase locked loop as claimed in claim 1, further comprising a state machine for continually monitoring and controlling the status of the loop.

Claim 10

A digital phase locked loop as claimed in claim 1, further comprising a fractional multiplier for deriving from the output of said digital controlled oscillator a further signal at a frequency which is a fraction of the output frequency of the digital controlled oscillator.

Claim 13

A method as claimed in claim 9, wherein said input signal is sampled with a circuit clocked by clock signals recovered by said loop.