Semiconductor integrated circuit device with reduced clock signal line noise

Claim 2

A macro-cell of a semiconductor integrated circuit, comprising: a clock signal line formed in a particular level interconnection layer of multi-level-layer interconnections of said macro-cell, for transmitting a clock signal; a first power-supply line formed in said particular level interconnection layer to be adjacent to said clock signal line, for supplying said macro-cell with a first power-supply potential; a second power-supply line for supplying said macro-cell with a second power-supply potential different from said first power-supply potential; a third power-supply line formed in said particular level interconnection layer to be adjacent to said clock signal line and supplied with either of said first and second power-supply potentials; and wherein said clock signal line is placed between said first power-supply line and said third power-supply line.

Claim 3

A semiconductor integrated circuit device having a circuit which is formed by employing a plurality of macro-cells, having data signal lines, and which operates on receiving a supply of a plurality of power-supply potentials and a clock signal, wherein each macro-cell comprises: a clock signal line formed in a particular level interconnection layer of multi-level-layer interconnections which transmits said clock signal; a first power-supply line for supplying each macro-cell with a first power-supply potential among said plurality of power-supply potentials; a second power-supply line formed in said particular level interconnection layer to be adjacent to said clock signal line and supplying each macro-cell with a second power-supply potential among said plurality of power-supply potentials; and a third power-supply line formed in said particular level interconnection layer to be adjacent to said clock signal line and receiving any one power-supply potential among said plurality of power-supply potentials; wherein none of said data signal lines are placed between said second power-supply line and said third power-supply line in said particular level interconnection layer.

Claim 4

A semiconductor integrated circuit device having a circuit which is formed by employing a plurality of macro-cells, having data signal lines, and which operates on receiving a supply of a plurality of power-supply potentials and a clock signal, wherein each macro-cell comprises: a clock signal line formed in a particular level interconnection layer of multi-level-layer interconnections which transmits said clock signal; a first power-supply line for supplying each macro-cell with a first power-supply potential among said plurality of power-supply potentials; a second power-supply line formed in said particular level interconnection layer to be adjacent to said clock signal line and supplying each macro-cell with a second power-supply potential among said plurality of power-supply potentials; and a third power-supply line formed in said particular level interconnection layer to be adjacent to said clock signal line and receiving any one power-supply potential among said plurality of power-supply potentials; wherein none of said data signal lines are placed between said second power-supply line and said third power-supply line in said particular level interconnection layer.

Claim 5

The semiconductor integrated circuit device of claim 2, wherein: said third power-supply line is supplied with said second power-supply potential.

Claim 6

The semiconductor integrated circuit device of claim 3, wherein: said second power-supply potential is higher than said first power-supply potential.

Claim 7

The semiconductor integrated circuit device of claim 4, wherein: at least one of said plurality of macro-cells includes an element which operates when an level of an inputted signal changes from a low level to a high level.

Claim 8

The semiconductor integrated circuit device of claim 4, wherein the circuit formed by employing at least one of said plurality of macro-cells includes an element which operates when a level of an inputted signal is at a higher level.

Claim 9

The semiconductor integrated circuit of claim 3, wherein said second power-supply potential is lower than said first power-supply potential.

Claim 10

The semiconductor integrated circuit device of claim 7, wherein the circuit formed by employing at least one of said plurality of macro-cells includes an element which operates when a level of an input signal changes from a higher level to a low level.

Claim 11

The semiconductor integrated circuit device of claim 7, wherein the circuit formed by employing at least one of said plurality of macro-cells includes an element which operates when a level of an input signal is at a lower level.

Claim 12

The semiconductor integrated circuit device of claim 3, wherein certain macro-cells comprise a connecting line which is formed in any one interconnection layer of said multi-level-layer interconnections different from said particular level interconnection layer and electrically connects said second power-supply line and said third power-supply line.

Claim 13

The semiconductor integrated circuit device of claim 3, wherein certain macro-cells comprise a connecting line which is formed in said particular level interconnection layer and electrically connects said second power-supply line and said third power-supply line.

Claim 14

The semiconductor integrated circuit device of claim 2, wherein said second power-supply line and said third-power supply line have different line widths.

Claim 15

The semiconductor integrated circuit device of claim 2, wherein: said plurality of macro cells includes first and second macro-cells which are used to construct desired first and second circuits, respectively; and said semiconductor integrated circuit device further comprising: a third macro-cell formed between said first and second macro cells, for wiring said first to third power-supply lines and said clock signal line of said first circuit to said first to third power-supply lines and said clock signal line of said second circuit, respectively.

Claim 16

The semiconductor integrated circuit device of claim 2, wherein at least one of said plurality of macro-cells includes a connecting line for electrically connecting between said gate electrodes of a pair of transistors, consisting of a PMOS transistor and an NMOS transistor, and said clock signal line.

Claim 17

The semiconductor integrated circuit device of claim 2, wherein said semiconductor integrated circuit device is constructed by a sea-of-gates array.

Claim 18

The semiconductor integrated circuit device of claim 2, wherein at least one of said plurality of macro-cells includes a connecting line for electrically connecting a gate electrode of a transistor thereof and said clock signal line.

Claim 19

The semiconductor integrated circuit device of claim 2, wherein said plurality of macro-cells are placed on a plurality of internal cell rows in a row direction.

Claim 20

The semiconductor integrated circuit device of claim 17, wherein: said clock signal line, said second power-supply line and said third power-supply line are placed in parallel in said row direction.