US5601678A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for providing electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
Assignee: 3M Co
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Filing: 1995-01-23
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Granted: 1997-02-11
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Expires: 2015-01-23
Abstract
Abstract A method of forming a multi-layer circuit board which includes electrical interconnections between adjacent circuit board layers of the multi-layer board. A via hole is provided through a circuit board layer. The via hole is filled with a via metal. The via metal is plated with a low melting point metal. An adhesive film is deposited over the circuit board layer. Adjacent layers of the multi-layer circuit board are stacked and aligned together. The layers are laminated under heat and pressure. The low melting point metal provides an electrical interconnection between adjacent layers.
Inventors
- 👤 Joel A. Gerber
- 👤 Peter A. Gits
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:20
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4611; H05K3/4614; H05K3/4617; H10; H10W; H10W99/00; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W90/401; H05K2201/00; H05K2201/01; H05K2201/0183; H05K2201/0195; H05K2201/03; H05K2201/0302; H05K2201/0305; H05K2201/0332; H05K2201/0388; H05K2201/0394; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/11; H05K2203/1189; H05K3/40; H05K3/4038; H05K3/42; H05K3/423; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
177 words
A method of making a multi-layer interconnect, comprising: depositing a trace metal layer on a first side of a first circuit board layer; forming a via hole extending between the first side and a second side of the first circuit board layer, wherein the via hole extends to the trace metal layer; depositing a via metal in the via hole such that said via metal forms a crown outward from said via hole on said second side of said first circuit board layer; depositing an electrical contact on a first side of a second circuit board layer; aligning the first circuit board layer with the second circuit board layer, wherein an adhesive is between the first and second circuit board layers and the electrical contact of the second circuit board layer is generally aligned with a via of the first circuit board layer; and laminating the first circuit board layer to the second circuit board layer wherein the via metal of the first circuit board layer electrically contacts the electrical contact of the second circuit board layer.
Claim 2
Independent Claim
177 words
A method of making a multi-layer interconnect, comprising: depositing a trace metal layer on a first side of a first circuit board layer; forming a via hole extending between the first side and a second side of the first circuit board layer, wherein the via hole extends to the trace metal layer; depositing a via metal in the via hole such that said via metal forms a crown outward from said via hole on said second side of said first circuit board layer; depositing an electrical contact on a first side of a second circuit board layer; aligning the first circuit board layer with the second circuit board layer, wherein an adhesive is between the first and second circuit board layers and the electrical contact of the second circuit board layer is generally aligned with a via of the first circuit board layer; and laminating the first circuit board layer to the second circuit board layer wherein the via metal of the first circuit board layer electrically contacts the electrical contact of the second circuit board layer.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein forming a via comprises wet or dry milling the first circuit board layer.
Claim 4
Dependent Claim
26 words
The method of claim 2 wherein the via is formed by wet milling, and wet milling comprises applying potassium hydroxide to the first circuit board layer.
Claim 5
Dependent Claim
30 words
The method of claim 2 wherein the via is formed by dry milling, and dry milling comprises using laser ablation to fabricate the holes in the first circuit board layer.
Claim 6
Dependent Claim
17 words
The method of claim 1 further comprising overplating the via metal with a low melting temperature metal.
Claim 7
Dependent Claim
18 words
The method of claim 5 wherein overplating with a low melting point metal layers comprises applying immersion tin.
Claim 8
Dependent Claim
15 words
The method of claim 5 wherein the low melting point metal layer comprises electroplated tin.
Claim 9
Dependent Claim
15 words
The method of claim 1 including applying heat and pressure during the step of laminating.
Claim 10
Dependent Claim
12 words
The method of claim 8 wherein the trace metal layer comprises copper.
Claim 11
Dependent Claim
28 words
The method of claim 1 wherein depositing an electrical contact comprises depositing a trace metal layer, the trace metal layer forming an electrical pad as the electrical contact.
Claim 12
Dependent Claim
11 words
The method of claim 1 wherein the via metal comprises copper.
Claim 13
Dependent Claim
22 words
The method of claim 1 including laminating at least a third circuit board layer to the first and second circuit board layers.
Claim 14
Independent Claim
287 words
A method for making a multi-layer interconnect, comprising: depositing a trace metal layer on a first side of a first circuit board layer; forming a via hole extending between the first side and a second side of the first circuit board layer, wherein the via hole extends to the trace metal layer; depositing a via metal in the via hole such that said via metal forms a crown outward from said via hole on said second side of said first circuit board layer; depositing a first electrical contact on a first side of a second circuit board layer, and a second electrical contact on a first side of a third circuit board layer; positioning the second circuit board layer adjacent the second side of the first circuit board layer and the third circuit board layer adjacent the first side of the first circuit board layer; aligning the first circuit board layer with the second circuit board layer and the third circuit board layer, wherein the electrical contact of the second circuit board layer is generally aligned with a via of the first circuit board layer and the electrical contact of the third circuit board layer is generally aligned with the trace metal on the first side of the first circuit board layer; providing an adhesive layer between at least the first circuit board layer and the second circuit board layer; and laminating the first circuit board layer to the second and third circuit board layers wherein the via metal of the first circuit board layer electrically contacts the electrical contact of the second circuit board layer, and the trace metal on the first circuit board layer electrically contacts the electrical contact on the third circuit board layer.
Claim 15
Independent Claim
287 words
A method for making a multi-layer interconnect, comprising: depositing a trace metal layer on a first side of a first circuit board layer; forming a via hole extending between the first side and a second side of the first circuit board layer, wherein the via hole extends to the trace metal layer; depositing a via metal in the via hole such that said via metal forms a crown outward from said via hole on said second side of said first circuit board layer; depositing a first electrical contact on a first side of a second circuit board layer, and a second electrical contact on a first side of a third circuit board layer; positioning the second circuit board layer adjacent the second side of the first circuit board layer and the third circuit board layer adjacent the first side of the first circuit board layer; aligning the first circuit board layer with the second circuit board layer and the third circuit board layer, wherein the electrical contact of the second circuit board layer is generally aligned with a via of the first circuit board layer and the electrical contact of the third circuit board layer is generally aligned with the trace metal on the first side of the first circuit board layer; providing an adhesive layer between at least the first circuit board layer and the second circuit board layer; and laminating the first circuit board layer to the second and third circuit board layers wherein the via metal of the first circuit board layer electrically contacts the electrical contact of the second circuit board layer, and the trace metal on the first circuit board layer electrically contacts the electrical contact on the third circuit board layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |