System and method for controlling assertion of a peripheral bus clock signal through a slave device

Claim 2

A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface unit coupled to said local bus and to said peripheral bus configured to control the transfer of data and address signals between said local bus and said peripheral bus; a clock generator circuit configured to provide a peripheral bus clock signal on said peripheral bus and further configured to selectively stop and re-start said peripheral bus clock signal; a clock control circuit coupled to said clock generator circuit wherein said clock control circuit is configured to generate a clock-off control signal to stop said peripheral bus clock signal upon an occurrence of a predetermined condition, and wherein said clock control circuit is configured to deassert a clock request signal at a clock request line prior to generating said clock-off control signal and stopping said peripheral bus clock signal; and a slave device coupled to said peripheral bus, wherein said slave device is configured to monitor said clock request line and wherein, if said clock request signal is deasserted, said clock control circuit is configured to assert said clock request signal if said peripheral bus clock signal is required by said slave device, wherein said clock control circuit is configured to delay the generation of said clock-off control signal for a predetermined time if said clock request signal is asserted by said slave device.

Claim 3

The computer system as recited in claim 1 wherein said slave device includes a state machine coupled to said clock request line, wherein said state machine is configured to detect the deassertion of said clock request signal and is configured to reassert said clock request signal if said peripheral bus clock signal is required by said slave device.

Claim 4

The computer system as recited in claim 1 further comprising an alternate bus master coupled to said peripheral bus wherein said alternate bus master is configured to assert said clock request signal when said peripheral bus clock signal is stopped, and wherein said clock control circuit is configured to generate a clock-on control signal that causes said peripheral bus clock signal to re-start in response to the assertion of the clock request signal.

Claim 5

The computer system as recited in claim 3 further comprising a bus arbiter unit coupled to said peripheral bus and configured to arbitrate mastership of said peripheral bus.

Claim 6

The computer system as recited in claim 3 further comprising a power management unit coupled to said clock control circuit and to said clock generator circuit, wherein said power management unit is configured to provide a control signal to said clock generator for selectively stopping and re-starting said peripheral bus clock signal, and wherein said clock control circuit is configured to provide said clock-on control signal to said power management unit in response to said clock request signal.

Claim 7

The computer system as recited in claim 5 wherein said power management unit is configured to stop said peripheral bus clock signal upon the occurrence of a predetermined condition after said microprocessor has attained mastership of said peripheral bus.

Claim 8

The computer system as recited in claim 1 wherein said peripheral bus is a PCI bus.

Claim 9

The computer system as recited in claim 1 wherein said clock request line is incorporated on said peripheral bus.

Claim 10

A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface unit coupled to said local bus and to said peripheral bus configured to control the transfer of data and address signals between said local bus and said peripheral bus; a clock generator circuit configured to provide a peripheral bus clock signal on said peripheral bus and further configured to selectively stop and re-start said peripheral bus clock signal; a clock control circuit coupled to said clock generator circuit wherein said clock control circuit is configured to generate a clock-off control signal to stop said peripheral bus clock signal upon an occurrence of a predetermined condition, and wherein said clock control circuit is configured to deassert a clock request signal at a clock request line prior to generating said clock-off control signal and stopping said peripheral bus clock signal; and a slave device coupled to said peripheral bus, wherein said slave device is configured to monitor said clock request line and wherein, if said clock request signal is deasserted, said clock control circuit is configured to assert said clock request signal if said peripheral bus clock signal is required by said slave device; and wherein said slave device includes a state machine coupled to said clock request line, wherein said state machine is configured to detect the deassertion of said clock request signal and is configured to reassert said clock request signal if said peripheral bus clock signal is required by said slave device; and wherein said clock control circuit includes a second state machine, wherein said second state machine is configured to deassert said clock request signal at said clock request line prior to generating said clock-off control signal, and wherein said second state machine is configured to delay the generation of said clock-off control signal for a predetermined time if said clock request signal is reasserted by said slave device and is configured to not delay the generation of said clock-off signal for said predetermined time if said clock request signal is not reasserted by said slave device.

Claim 11

A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface unit coupled to said local bus and to said peripheral bus configured to control the transfer of data and address signals between said local bus and said peripheral bus; a clock generator circuit configured to provide a peripheral bus clock signal on said peripheral bus and further configured to selectively stop and re-start said peripheral bus clock signal; a clock control circuit coupled to said clock generator circuit wherein said clock control circuit is configured to generate a clock-off control signal to stop said peripheral bus clock signal upon an occurrence of a predetermined condition, and wherein said clock control circuit is configured to deassert a clock request signal at a clock request line prior to generating said clock-off control signal and stopping said peripheral bus clock signal; and a slave device coupled to said peripheral bus, wherein said slave device is configured to monitor said clock request line and wherein, if said clock request signal is deasserted, said clock control circuit is configured to assert said clock request signal if said peripheral bus clock signal is required by said slave device; and wherein said slave device includes a state machine coupled to said clock request line, wherein said state machine is configured to detect the deassertion of said clock request signal and is configured to reassert said clock request signal if said peripheral bus clock signal is required by said slave device; and wherein said clock control circuit includes a second state machine, wherein said second state machine is configured to deassert said clock request signal at said clock request line prior to generating said clock-off control signal, and wherein said second state machine is configured to delay the generation of said clock-off control signal for a predetermined time if said clock request signal is reasserted by said slave device and is configured to not delay the generation of said clock-off signal for said predetermined time if said clock request signal is not reasserted by said slave device.

Claim 12

A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface unit coupled to said local bus and to said peripheral bus configured to control the transfer of data and address signals between said local bus and said peripheral bus; a bus arbiter unit coupled to said peripheral bus and configured to arbitrate mastership of said peripheral bus; a clock generator circuit configured to provide a peripheral bus clock signal on said peripheral bus and further configured to selectively stop and re-start said peripheral bus clock signal; a clock control circuit coupled to said clock generator circuit wherein said clock control circuit is configured to generate a clock-off control signal to stop said peripheral bus clock signal upon an occurrence of a predetermined condition, and wherein said clock control circuit is configured to deassert a clock request signal at a clock request line prior to generating said clock-off control signal and stopping said peripheral bus clock signal; a slave device coupled to said peripheral bus, wherein said slave device is configured to monitor said clock request line and wherein, if said clock request signal is deasserted, said clock control circuit is configured to assert said clock request signal if said peripheral bus clock signal is required by said slave device; and an alternate bus master coupled to said peripheral bus wherein said alternate bus master is configured to assert said clock request signal when said peripheral bus clock signal is stopped, and wherein said clock control circuit is configured to generate a clock-on control signal that causes said peripheral bus clock signal to re-start in response to the assertion of the clock request signal; wherein said alternate bus master includes a third state machine that is configured to assert said clock request signal when said peripheral bus clock signal is stopped and is configured to assert a synchronous bus request signal after said peripheral bus clock signal is re-started, wherein said synchronous bus request signal is provided to said bus arbiter unit for requesting mastership of said peripheral bus.

Claim 13

A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface unit coupled to said local bus and to said peripheral bus configured to control the transfer of data and address signals between said local bus and said peripheral bus; a bus arbiter unit coupled to said peripheral bus and configured to arbitrate mastership of said peripheral bus; a clock generator circuit configured to provide a peripheral bus clock signal on said peripheral bus and further configured to selectively stop and re-start said peripheral bus clock signal; a clock control circuit coupled to said clock generator circuit wherein said clock control circuit is configured to generate a clock-off control signal to stop said peripheral bus clock signal upon an occurrence of a predetermined condition, and wherein said clock control circuit is configured to deassert a clock request signal at a clock request line prior to generating said clock-off control signal and stopping said peripheral bus clock signal; a slave device coupled to said peripheral bus, wherein said slave device is configured to monitor said clock request line and wherein, if said clock request signal is deasserted, said clock control circuit is configured to assert said clock request signal if said peripheral bus clock signal is required by said slave device; and an alternate bus master coupled to said peripheral bus wherein said alternate bus master is configured to assert said clock request signal when said peripheral bus clock signal is stopped, and wherein said clock control circuit is configured to generate a clock-on control signal that causes said peripheral bus clock signal to re-start in response to the assertion of the clock request signal; wherein said alternate bus master includes a third state machine that is configured to assert said clock request signal when said peripheral bus clock signal is stopped and is configured to assert a synchronous bus request signal after said peripheral bus clock signal is re-started, wherein said synchronous bus request signal is provided to said bus arbiter unit for requesting mastership of said peripheral bus.

Claim 14

The computer system as recited in claim 10 wherein said bus arbiter unit is configured to assert a bus grant signal in response to said synchronous bus request signal.

Claim 17

The system for controlling a peripheral bus clock signal as recited in claim 12 wherein said state machine of said clock control circuit is configured to deassert said clock request signal prior to deasserting said ON/OFF signal.

Claim 18

The system for controlling a peripheral bus clock signal as recited in claim 13 wherein said state machine of said clock control circuit is configured to deassert said ON/OFF signal to stop said peripheral bus clock signal if said clock request signal is not reasserted by said slave device within a second predetermined time after said clock request signal is deasserted by said state machine.

Claim 19

The system for controlling a peripheral bus clock signal as recited in claim 12 wherein said peripheral bus is a PCI standard bus.

Claim 20

The system for controlling a peripheral bus clock signal as recited in claim 12 further comprising a control line incorporated on said peripheral bus configured to couple said clock request signal between said clock control circuit and said slave device.

Claim 23

The method for controlling a peripheral bus clock signal as recited in claim 17 further comprising the step of providing said indicator signal on a control line of said peripheral bus.