Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer

Claim 2

A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with said data bus at a second clock frequency, said communication system comprising: clock generation means for generating a bus clock signal at said first clock frequency and a chip clock signal at said second clock frequency wherein said first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein said bus and chip clock signals are synchronized once every N cycles of said chip clock signal; means for generating asynchronization signal indicating said chip clock signal cycle in which said bus and chip clock signals are synchronized; means, connected to said circuit block, for receiving data from said bus; means, connected to said circuit block, for transmitting data on said bus; means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which data cannot be transmitted by said circuit block on said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles; and means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which no new data can be received from said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles, wherein said receiving means comprises: a first register connected to receive data from said bus, said first register being synchronized to said bus clock signal; and a latch synchronized to said chip clock signal.

Claim 3

A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with said data bus at a second clock frequency, said communication system comprising: clock generation means for generating a bus clock signal at said first clock frequency and a chip clock signal at said second clock frequency wherein said first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein said bus and chip clock signals are synchronized once every N cycles of said chip clock signal; means for generating a synchronization signal indicating said chip clock signal cycle in which said bus and chip clock signals are synchronized; means, connected to said circuit block, for receiving data from said bus; means, connected to said circuit block, for transmitting data on said bus; means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which data cannot be transmitted by said circuit block on said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles; and means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which no new data can be received from said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles, wherein said receiving means comprises a first register connected to receive data from said bus, said first register being synchronized to said bus clock signal and a latch synchronized to said chip clock signal, and wherein said first register comprises: a first latch reading data from said bus in response to said bus clock signal; and a second latch in series with said first latch, said second latch receiving data from said first latch in response to a transfer signal such that said second latch is prevented from updating while the state of said first latch is changing.

Claim 4

A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with said data bus at a second clock frequency, said communication system comprising: clock generation means for generating a bus clock signal at said first clock frequency and a chip clock signal at said second clock frequency wherein said first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein said bus and chip clock signals are synchronized once every N cycles of said chip clock signal; means for generating a synchronization signal indicating said chip clock signal cycle in which said bus and chip clock signals are synchronized; means, connected to said circuit block, for receiving data from said bus; means, connected to said circuit block, for transmitting data on said bus; means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which data cannot be transmitted by said circuit block on said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles; and means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which no new data can be received from said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles, wherein said receiving means comprises a first register connected to receive data from said bus, said first register being synchronized to said bus clock signal and a latch synchronized to said chip clock signal, and wherein said first register comprises: a first latch reading data from said bus in response to said bus clock signal; and a second latch in series with said first latch, said second latch receiving data from said first latch in response to a transfer signal such that said second latch is prevented from updating while the state of said first latch is changing.

Claim 5

A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with said data bus at a second clock frequency, said communication system comprising: clock generation means for generating a bus clock signal at said first clock frequency and a chip clock signal at said second clock frequency wherein said first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein said bus and chip clock signals are synchronized once every N cycles of said chip clock signal; means for generating a synchronization signal indicating said chip clock signal cycle in which said bus and chip clock signals are synchronized: means, connected to said circuit block, for receiving data from said bus; means, connected to said circuit block, for transmitting data on said bus; means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which data cannot be transmitted by said circuit block on said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles; and means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which no new data can be received from said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles, wherein said transmitting means comprises: a latch synchronized to said chip clock signal and connected to receive data from said circuit block; and a first register connected to transmit data on said bus, said first register being synchronized to said bus clock signal and being connected to the output of said latch.

Claim 6

A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with said data bus at a second clock frequency, said communication system comprising: clock generation means for generating a bus clock signal at said first clock frequency and a chip clock signal at said second clock frequency wherein said first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein said bus and chip clock signals are synchronized once every N cycles of said chip clock signal; means for generating a synchronization signal indicating said chip clock signal cycle in which said bus and chip clock signals are synchronized: means, connected to said circuit block, for receiving data from said bus; means, connected to said circuit block, for transmitting data on said bus; means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which data cannot be transmitted by said circuit block on said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles; and means, connected to said circuit block and responsive to said synchronization signal, for identifying a chip clock signal cycle in which no new data can be received from said bus, one said chip clock signal cycle being present in each contiguous block of N said chip clock cycles, wherein said transmitting means comprises: a latch synchronized to said chip clock signal and connected to receive data from said circuit block; and a first register connected to transmit data on said bus, said first register being synchronized to said bus clock signal and being connected to the output of said latch.

Claim 7

The data communication system of claim 3 further comprising means, connected to said latch, for preventing said latch from updating while said register is changing state.