US5600604A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for allowing a simm module with asymmetric addressing to be utilized in a computer system
Assignee: Advanced Peripherals Labs Inc
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Filing: 1995-05-01
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Granted: 1997-02-04
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Expires: 2015-05-01
Abstract
Abstract A circuit for allowing a memory module with an asymmetric addressing scheme to effectively operate with a memory controller which a symmetric address scheme is disclosed. The circuit includes a demultiplexer for receiving at least a last address bit from the memory controller and generating a plurality of control signals and a decoder. The decoder includes a plurality of decoder units. Each of the decoder units includes logic for receiving one of the plurality of control signals, a first strobe signal and a second strobe signal from the memory controller. Each of the decoder units also selectably provides a decoded second strobe signal responsive to the demultiplexer.
Inventors
- 👤 Roger Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C8/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
112 words
A circuit for allowing a memory module with an asymmetric addressing scheme to effectively operate with a memory controller which has a symmetric address scheme, the circuit comprising: a demultiplexer means for receiving at least the last address bit of address signals from the memory controller and generating a plurality of control signals; and a decoder means, the decoder means including a plurality of decoder units, each of the decoder units comprising logic means for receiving one of the plurality of control signals, two address strobe signals from the memory controller, each of the decoder units selectably providing a decoded one of the two address strobe signals responsive to the demultiplexer means.
Claim 2
Dependent Claim
112 words
A circuit for allowing a memory module with an asymmetric addressing scheme to effectively operate with a memory controller which has a symmetric address scheme, the circuit comprising: a demultiplexer means for receiving at least the last address bit of address signals from the memory controller and generating a plurality of control signals; and a decoder means, the decoder means including a plurality of decoder units, each of the decoder units comprising logic means for receiving one of the plurality of control signals, two address strobe signals from the memory controller, each of the decoder units selectably providing a decoded one of the two address strobe signals responsive to the demultiplexer means.
Claim 3
Dependent Claim
26 words
The circuit of claim 1 in which the two address strobe signals comprises a row address strobe (RAS) signal and a column address strobe (CAS) signal.
Claim 4
Dependent Claim
40 words
The circuit of claim 2 in which each of the decoder units comprises: decoder circuit for receiving the RAS and CAS signals and providing output signal; and transmission gate for holding the output signal and providing a decoded CAS signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |