US5392252A
Expired / Lapsed
US
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Programmable memory addressing
Assignee: Philips Semiconductors Inc
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Filing: 1990-11-13
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Granted: 1995-02-21
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Expires: 2010-11-13
Abstract
Abstract A software programmable memory addressing system operates with multiple banks of DRAM chips. The DRAM chips in the different banks may be of different sizes and may be located physically in arrangements where the largest memory chips are not necessarily placed in the first memory bank. The system permits 256K, 1M, and 4M DRAMs to be supported separately, and in combinations of any two of the three types. An internal DRAM controller generates row address strobes (RAS) and column address strobes (CAS) which are supplied to a multiplexer switch bank for routing the RAS and CAS strobes to the physical DRAM banks according to a program set in a register used to control the operation of the multiplexers. Consequently, internally generated logical RAS and CAS signals are routed to the appropriate physical banks of DRAM to create a valid memory map, without requiring the physical arrangement of the banks of DRAMs in a pre-established order.
Inventors
- 👤 Charles R. Rimpo
- 👤 Walter H. Potts
- 👤 Joe A. Thomsen
- 👤 Mitch A. Stones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:24
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
184 words
A memory addressing system for a computer memory having a plurality of memory banks of memory devices of different sizes, which may be arranged physically in said memory banks in any desired order, said addressing system including in combination: means for supplying a plurality of different row and column address signals to said memory banks; memory map means pre-encoded with a memory map corresponding to the physical arrangement of said memory devices and coupled with said row and column address signal supply means for supplying at least row and column address signals corresponding to logical memory bank outputs; switching control means comprising a plurality of multiplexers each connected to a different one of said plurality of memory banks for interconnecting said logical memory bank outputs with selected ones of said memory banks to create a valid programmable memory map irrespective of the actual locations of memory devices of different sizes in said memory banks; and a multiplex code register coupled with said multiplexers for routing said logical memory bank outputs through said multiplexers to said memory banks as determined by said multiplex code register.
Claim 2
Dependent Claim
184 words
A memory addressing system for a computer memory having a plurality of memory banks of memory devices of different sizes, which may be arranged physically in said memory banks in any desired order, said addressing system including in combination: means for supplying a plurality of different row and column address signals to said memory banks; memory map means pre-encoded with a memory map corresponding to the physical arrangement of said memory devices and coupled with said row and column address signal supply means for supplying at least row and column address signals corresponding to logical memory bank outputs; switching control means comprising a plurality of multiplexers each connected to a different one of said plurality of memory banks for interconnecting said logical memory bank outputs with selected ones of said memory banks to create a valid programmable memory map irrespective of the actual locations of memory devices of different sizes in said memory banks; and a multiplex code register coupled with said multiplexers for routing said logical memory bank outputs through said multiplexers to said memory banks as determined by said multiplex code register.
Claim 3
Dependent Claim
23 words
The combination according to claim 1 wherein said memory devices comprise combinations of any two of 256K chips, 1M chips and 4M chips.
Claim 4
Dependent Claim
12 words
The process according to claim 2 wherein said memory devices are DRAMS.
Claim 5
Dependent Claim
12 words
The process according to claim 1 wherein said memory devices are DRAMS.
Claim 6
Dependent Claim
109 words
A process of addressing a memory system having a plurality of memory banks of memory devices of different sizes comprising the steps of: providing N memory banks in predetermined physical locations in which memory devices of different sizes may be located in any of said N memory banks; establishing a memory map for supplying address signals corresponding to logical memory bank outputs; providing a multiplex switch interface between said logical memory bank outputs and said memory banks; and programming said multiplex switch means to re-route any one of said logical memory bank outputs to any selected one of said N memory banks in accordance with a pre-established re-routing code.
Claim 7
Dependent Claim
109 words
A process of addressing a memory system having a plurality of memory banks of memory devices of different sizes comprising the steps of: providing N memory banks in predetermined physical locations in which memory devices of different sizes may be located in any of said N memory banks; establishing a memory map for supplying address signals corresponding to logical memory bank outputs; providing a multiplex switch interface between said logical memory bank outputs and said memory banks; and programming said multiplex switch means to re-route any one of said logical memory bank outputs to any selected one of said N memory banks in accordance with a pre-established re-routing code.
Claim 8
Dependent Claim
36 words
The process according to claim 5 further comprising the step of encoding the operation of said multiplex switch means in accordance with the sizes of the memory devices stored in each of said N memory banks.
Claim 9
Dependent Claim
12 words
The process according to claim 6 wherein said memory devices are DRAMS.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-20 | 1998-08-22 | 1999-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-20 | 2002-08-22 | 2003-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-20 | 2006-08-22 | 2007-02-21 | $7700.00 | Window Closed / Lapsed |