Constant delay logic circuits and methods

Claim 2

A constant delay logic element with an input for receiving an input signal and an output for outputting an output signal comprising: a single constant current source, switching transistors coupled to the current source, inputs coupled to the switching transistors for applying input signals to the switching transistors, current load devices coupled to the switching transistors, outputs coupled to the load devices for outputting signals from the load devices, said switching transistors steering current among said load devices in accordance with the input signals applied to said switching transistors, means, coupled to the constant current source, for controlling the magnitude of the constant current, means responsive to the magnitude of the constant current for delaying the propagation of a signal from the input to the output inversely proportional to the magnitude of the constant current, whereby said propagation delay is determined by the current source.

Claim 3

A constant delay logic element with an input for receiving an input signal and an output for outputting an output signal comprising: a constant current source, switching transistors coupled to the current source, inputs coupled to the switching transistors for applying input signals to the switching transistors, current load devices coupled to the switching transistors, outputs coupled to the load devices for outputting signals from the load devices, said switching transistors steering current among said load devices in accordance with the input signals applied to said switching transistors, means, coupled to the constant current source, for controlling the magnitude of the constant current, means responsive to the magnitude of the constant current for delaying the propagation of a signal from the input to the output inversely proportional to the magnitude of the constant current, and wherein said constant current source has a bias voltage, means responsive to said bias voltage for propagating a signal through said logic element at a speed proportional to said bias voltage, and means for controlling the magnitude of the bias voltage to fix the delay of a signal through said logic element.

Claim 4

A constant delay logic element with an input for receiving an input signal and an output for outputting an output signal comprising: a constant current source, switching transistors coupled to the current source, inputs coupled to the switching transistors for applying input signals to the switching transistors, current load devices coupled to the switching transistors, outputs coupled to the load devices for outputting signals from the load devices, said switching transistors steering current among said load devices in accordance with the input signals applied to said switching transistors, means, coupled to the constant current source, for controlling the magnitude of the constant current, means responsive to the magnitude of the constant current for delaying the propagation of a signal from the input to the output inversely proportional to the magnitude of the constant current, and wherein said constant current source has a bias voltage, means responsive to said bias voltage for propagating a signal through said logic element at a speed proportional to said bias voltage, and means for controlling the magnitude of the bias voltage to fix the delay of a signal through said logic element.

Claim 5

The logic element of claim 2 wherein the means for controlling the bias voltage comprises a phase locked loop.

Claim 6

The logic element of claim 3 wherein the phase locked loop comprises a voltage controlled oscillator having a plurality of said logic elements.

Claim 7

The logic element of claim 4 wherein the number of logic elements comprising a voltage controlled oscillator is an odd number.

Claim 8

The logic element of claim 3 wherein the phase locked loop comprises a voltage control oscillator, a phase comparator and a reference oscillator wherein said voltage controlled oscillator and said reference oscillator are each coupled to said phase comparator, and wherein the output of the phase comparator provides the bias voltage.

Claim 9

A reference voltage generator comprising: a phase locked loop with a ring oscillator, said ring oscillator comprising a plurality of series connected constant delay logic inverters, all of said constant delay logic inverters coupled to a reference voltage bias source and each inverter having a constant delay dependent upon the magnitude of the reference bias voltage for generating a ring oscillator frequency representative of the reference voltage bias source; a reference oscillator generating a signal at a reference frequency, a phase comparator for comparing the frequency of the ring oscillator and the frequency of the reference oscillator and generating a phase comparator output signal representative of said comparison between the reference frequency and the ring oscillator frequency, a loop filter coupled to the phase comparator output signal for filtering the output signal of the phase comparator to provide a filtered output signal representative of the difference in frequency between the ring oscillator and the reference oscillator, and an amplifier coupled to the output of the loop filter for generating the reference voltage bias source.

Claim 10

A reference voltage generator comprising: a phase locked loop with a ring oscillator, said ring oscillator comprising a plurality of series connected constant delay logic inverters, all of said constant delay logic inverters coupled to a reference voltage bias source and each inverter having a constant delay dependent upon the magnitude of the reference bias voltage for generating a ring oscillator frequency representative of the reference voltage bias source; a reference oscillator generating a signal at a reference frequency, a phase comparator for comparing the frequency of the ring oscillator and the frequency of the reference oscillator and generating a phase comparator output signal representative of said comparison between the reference frequency and the ring oscillator frequency, a loop filter coupled to the phase comparator output signal for filtering the output signal of the phase comparator to provide a filtered output signal representative of the difference in frequency between the ring oscillator and the reference oscillator, and an amplifier coupled to the output of the loop filter for generating the reference voltage bias source.

Claim 11

A constant delay logic system comprising: a first plurality of logic elements, each logic element coupled to a voltage bias and each logic element having a delay time inversely proportional to the magnitude of the voltage bias; a phase locked loop comprising a voltage controlled oscillator having a second plurality of logic elements, each of said second plurality of logic elements having a delay time inversely proportional to the magnitude of the voltage bias and for oscillating at a frequency determined by the delay times of the second plurality of logic elements, a reference oscillator for oscillating any reference frequency, comparing means, coupled to the voltage controlled oscillator and the reference oscillator, for comparing the frequency of the voltage controlled oscillator to the frequency of the reference oscillator, means responsive to said comparing means and coupled to said comparing means and the voltage controlled oscillator for providing a voltage bias signal to the voltage controlled oscillator for operating the voltage controlled oscillator at a frequency corresponding to the frequency of the reference oscillator; and means for coupling the voltage bias signal to the first plurality of logic elements.

Claim 12

A constant delay logic system comprising: a first plurality of logic elements, each logic element coupled to a voltage bias and each logic element having a delay time inversely proportional to the magnitude of the voltage bias; a phase locked loop comprising a voltage controlled oscillator having a second plurality of logic elements, each of said second plurality of logic elements having a delay time inversely proportional to the magnitude of the voltage bias and for oscillating at a frequency determined by the delay times of the second plurality of logic elements, a reference oscillator for oscillating any reference frequency, comparing means, coupled to the voltage controlled oscillator and the reference oscillator, for comparing the frequency of the voltage controlled oscillator to the frequency of the reference oscillator, means responsive to said comparing means and coupled to said comparing means and the voltage controlled oscillator for providing a voltage bias signal to the voltage controlled oscillator for operating the voltage controlled oscillator at a frequency corresponding to the frequency of the reference oscillator; and means for coupling the voltage bias signal to the first plurality of logic elements.

Claim 13

A clock signal generator comprising a phase locked loop with a voltage controlled oscillator comprising an odd plurality of series connected inverters wherein each inverter has a delay dependent upon an applied bias voltage and means for comparing a reference frequency to the frequency of the voltage controlled oscillator to generate a said bias voltage; means coupled to a first pair of said inverters for generating a first output clock signal and means coupled to a second pair of said inverters for generating a second output clock signal displaced in phase from said first clock signal.

Claim 14

A clock signal generator comprising a phase locked loop with a voltage controlled oscillator comprising an odd plurality of series connected inverters wherein each inverter has a delay dependent upon an applied bias voltage and means for comparing a reference frequency to the frequency of the voltage controlled oscillator to generate a said bias voltage; means coupled to a first pair of said inverters for generating a first output clock signal and means coupled to a second pair of said inverters for generating a second output clock signal displaced in phase from said first clock signal.

Claim 15

The clock signal generator of claim 9 wherein said first and second clock signals have the same frequency.

Claim 16

The clock signal generator of claim 9 comprising means coupled to a third pair of inverters for generating a third output clock signal displaced in phase from said first and second clock signals and having the same frequency as said first and second clock signals.

Claim 17

A clock signal generator comprising an odd plurality of series connected inverters wherein each inverter comprises a current steering circuit, a constant current source, a bias voltage source for controlling a constant delay dependent upon the bias voltage.

Claim 18

A clock signal generator comprising an odd plurality of series connected inverters wherein each inverter comprises a current steering circuit, a constant current source, a bias voltage source for controlling a constant delay dependent upon the bias voltage.