Patent US5600168A successfully refreshed from Google Patents.
US5600168A
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US
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Semiconductor element and method for fabricating the same
Assignee: SK Hynix Inc
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Filing: 1995-08-03
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Granted: 1997-02-04
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Expires: 2015-08-03
Abstract
Abstract This invention relates to MOS transistors and a method for fabricating the MOS transistors having LDD (Lightly Doped Drain) structures, which comprises a first conduction type semiconductor substrate, a second conduction type high density source and drain regions formed spaced from each other in the first conduction type semiconductor substrate, a second conduction type low density impurity region formed on sides facing each other of, and adjacent to the second conduction type high density source and drain regions, a first gate insulation film formed on both ends of a upper part of the semiconductor substrate region between the second conduction type low density impurity region, a second gate insulation film formed on upper part of the semiconductor substrate region between the first gate insulation films, a first conduction layer in a form of side wall spacer formed on the first gate insulation film, a second conduction layer formed on the second gate insulation film, a third conduction layer formed on the first conduction layer and the second conduction layer, insulation film side wall spacers formed on sides of the first conduction film and the third conduction layer, and a punch through prevention region formed in a semiconductor substrate region beneath the second gate insulation film.
Inventors
- 👤 Bong J. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01322; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10D30/60; H10D30/601; Y; Y10; Y10S; Y10S257/00; Y10S257/90; Y10S257/92
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
181 words
A semiconductor element comprising: a first conductivity-type semiconductor substrate; second conductivity-type high-density source and drain regions formed spaced from each other in the semiconductor substrate; a second conductivity-type low-density impurity region formed adjacent to the second conductivity-type high-density source and drain regions; pair of first gate insulation films formed on both ends of the semiconductor substrate between the second conductivity-type low-density impurity region; a second gate insulation film formed on the semiconductor substrate between the pair of first gate insulation films; a pair of first conduction layers in the form of a sidewall spacer formed directly above the first gate insulation films; a second conduction layer formed on the second gate insulation film; a third conduction layer connecting the pair of first conduction layers and the second conduction layer so as to form a single gate; an insulation film sidewall spacer in contact with one of the pair of first gate insulation films and the first and one of the pair third conduction layers; and a punch through prevention impurity region formed in the semiconductor substrate beneath the second conduction layer.
Claim 2
Dependent Claim
181 words
A semiconductor element comprising: a first conductivity-type semiconductor substrate; second conductivity-type high-density source and drain regions formed spaced from each other in the semiconductor substrate; a second conductivity-type low-density impurity region formed adjacent to the second conductivity-type high-density source and drain regions; pair of first gate insulation films formed on both ends of the semiconductor substrate between the second conductivity-type low-density impurity region; a second gate insulation film formed on the semiconductor substrate between the pair of first gate insulation films; a pair of first conduction layers in the form of a sidewall spacer formed directly above the first gate insulation films; a second conduction layer formed on the second gate insulation film; a third conduction layer connecting the pair of first conduction layers and the second conduction layer so as to form a single gate; an insulation film sidewall spacer in contact with one of the pair of first gate insulation films and the first and one of the pair third conduction layers; and a punch through prevention impurity region formed in the semiconductor substrate beneath the second conduction layer.
Claim 3
Dependent Claim
23 words
The semiconductor element as claimed in claim 1, wherein the first gate insulation films and the second gate insulation film have different thicknesses.
Claim 4
Dependent Claim
24 words
The semiconductor element as claimed in claim 1, wherein the second gate insulation film is thicker than each of the first gate insulation films.
Claim 5
Dependent Claim
36 words
The semiconductor element as claimed in claim 1, wherein the second gate insulation film is formed on an upper part of the semiconductor substrate between the first gate insulation films and on the first conduction layers.
Claim 6
Dependent Claim
17 words
The semiconductor element as claimed in claim 1, wherein the third conduction layer is formed of salicide.
Claim 7
Independent Claim
272 words
A method for fabricating a semiconductor element, comprising the steps of: forming a buffer layer on a first conductivity-type semiconductor substrate; forming an insulation film on the buffer layer; coating photoresist on the insulation film; exposing a gate pole forming area by removing the insulation film and the buffer layer selectively using the photoresist as a mask; removing the photoresist; forming a first gate insulation film on the exposed semiconductor substrate area; forming a first conduction layer in the form of a sidewall directly above the first gate insulation film by carrying out deposition and etch back of conduction material on all over the surface of the first gate insulation film and the insulation film; forming a second gate insulation film on the semiconductor substrate area exposed by the etching of the first gate insulation film and on the first conduction layer; forming a punch-through prevention region in the semiconductor substrate beneath the second gate insulation film by ion injection of first conductivity-type impurities in low density; forming a second conduction layer on the second gate insulation film; forming a third conduction layer on top of the exposed first conduction layer and the second conduction layer; removing the insulation film and the buffer layer successively; forming a low-density impurity region in a predetermined area of the semiconductor substrate by ion injecting second conductivity-type impurities in low density; forming an insulation sidewall spacer in contact with the first gate insulation film and the first and third conduction layers; and forming high density source and drain regions in predetermined areas of the semiconductor substrate by ion injection of second conductivity-type impurities in high density.
Claim 8
Independent Claim
272 words
A method for fabricating a semiconductor element, comprising the steps of: forming a buffer layer on a first conductivity-type semiconductor substrate; forming an insulation film on the buffer layer; coating photoresist on the insulation film; exposing a gate pole forming area by removing the insulation film and the buffer layer selectively using the photoresist as a mask; removing the photoresist; forming a first gate insulation film on the exposed semiconductor substrate area; forming a first conduction layer in the form of a sidewall directly above the first gate insulation film by carrying out deposition and etch back of conduction material on all over the surface of the first gate insulation film and the insulation film; forming a second gate insulation film on the semiconductor substrate area exposed by the etching of the first gate insulation film and on the first conduction layer; forming a punch-through prevention region in the semiconductor substrate beneath the second gate insulation film by ion injection of first conductivity-type impurities in low density; forming a second conduction layer on the second gate insulation film; forming a third conduction layer on top of the exposed first conduction layer and the second conduction layer; removing the insulation film and the buffer layer successively; forming a low-density impurity region in a predetermined area of the semiconductor substrate by ion injecting second conductivity-type impurities in low density; forming an insulation sidewall spacer in contact with the first gate insulation film and the first and third conduction layers; and forming high density source and drain regions in predetermined areas of the semiconductor substrate by ion injection of second conductivity-type impurities in high density.
Claim 9
Dependent Claim
18 words
The method as claimed in claim 6, wherein the buffer layer is formed of a silicon oxide film.
Claim 10
Dependent Claim
34 words
The method as claimed in claim 6, wherein the insulation film is formed of a material having an etch selectivity over the first conduction layer, the second conduction layer and the third conduction layer.
Claim 11
Dependent Claim
16 words
The method as claimed in claim 6, wherein the insulation film comprises a silicon oxide film.
Claim 12
Dependent Claim
20 words
The method as claimed in claim 6, wherein the first gate insulation film is formed by a thermal oxidation process.
Claim 13
Dependent Claim
16 words
The method as claimed in claim 6, wherein the first conduction layer is formed of polysilicon.
Claim 14
Dependent Claim
20 words
The method as claimed in claim 6, wherein the second gate insulation film is formed by a thermal oxidation process.
Claim 15
Dependent Claim
16 words
The method as claimed in claim 6, wherein the second conduction layer is formed of polysilicon.
Claim 16
Dependent Claim
16 words
The method as claimed in claim 6, wherein the third conduction layer is formed of salicide.
Claim 17
Dependent Claim
139 words
A semiconductor element comprising: a first conductivity-type substrate; a first gate insulation film formed on the substrate; a pair of first conduction layers formed including two opposite sidewall spacers directly above the first gate insulation film; a second gate insulation film formed on the first conduction layer; a second conduction layer formed on the second gate insulation film; a third conduction layer connecting the first and second conduction layers so as to form a single gate; a punch through prevention impurity region formed in the semiconductor substrate beneath the second conduction layer; and a pair of insulation sidewall spacer including two opposite sidewall spacers at the sidewall of the first gate insulation film, the first conduction layer and the third conduction layer; and second conductivity-type source and drain regions formed in the substrate adjacent to the insulation sidewall spacer.
Claim 18
Dependent Claim
139 words
A semiconductor element comprising: a first conductivity-type substrate; a first gate insulation film formed on the substrate; a pair of first conduction layers formed including two opposite sidewall spacers directly above the first gate insulation film; a second gate insulation film formed on the first conduction layer; a second conduction layer formed on the second gate insulation film; a third conduction layer connecting the first and second conduction layers so as to form a single gate; a punch through prevention impurity region formed in the semiconductor substrate beneath the second conduction layer; and a pair of insulation sidewall spacer including two opposite sidewall spacers at the sidewall of the first gate insulation film, the first conduction layer and the third conduction layer; and second conductivity-type source and drain regions formed in the substrate adjacent to the insulation sidewall spacer.
Claim 19
Dependent Claim
98 words
A semiconductor device comprising: a substrate; a source region in the substrate; a drain region in the substrate spaced from the drain region; a pair of first gate insulation films on respective ends of the substrate between the source and drain regions; a second gate insulation film on the substrate disposed between the pair of first gate insulation films; a pair of first conduction layers on the pair of first gate insulation films; a second conduction layer on the second gate insulation film; and a third conduction layer connecting the first conduction layers and the second conduction layer.
Claim 20
Dependent Claim
98 words
A semiconductor device comprising: a substrate; a source region in the substrate; a drain region in the substrate spaced from the drain region; a pair of first gate insulation films on respective ends of the substrate between the source and drain regions; a second gate insulation film on the substrate disposed between the pair of first gate insulation films; a pair of first conduction layers on the pair of first gate insulation films; a second conduction layer on the second gate insulation film; and a third conduction layer connecting the first conduction layers and the second conduction layer.
References Cited (Backward Citations)
US5027185A
Cited
US5047816A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |