Array with metal scan lines controlling semiconductor gate lines

Claim 2

An array comprising: a substrate with a surface at which circuitry can be formed; and array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of M scan lines, where M is greater than 1; each of the scan lines extending approximately in a first direction across the surface of the substrate; the M scan lines being positioned in order from first through Mth; a set of N data lines, where N is greater than 1; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being different than the first direction; the N data lines being positioned in order from first through Nth; for each value of m from 1 through M and for each value of n from 1 through N, a crossing region in which the mth scan line and the nth data line cross; for each of a set of one or more of the crossing regions, cell circuitry connected to the mth scan line and the nth data line; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from or providing signals to the nth data line; and connecting circuitry for electrically connecting the data lead to the nth data line under control of the mth scan line; the mth scan line comprising metal; the connecting circuitry comprising: a first semiconductor line connected between the nth data line and the data lead; the first semiconductor line including a first channel; and a second semiconductor line connected to the mth scan line and crossing the first semiconductor line at the first channel; the second semiconductor line being conductive so that signals on the mth scan line control conductivity of the first channel.

Claim 3

The array of claim 1 in which the first and second directions are perpendicular.

Claim 4

The array of claim 1 in which the array is a two-dimensional array.

Claim 5

The array of claim 1 in which the substrate is an insulating substrate.

Claim 6

The array of claim 1 in which the array circuitry comprises a thin-film structure.

Claim 7

The array of claim 1 in which the first semiconductor line comprises polysilicon.

Claim 8

The array of claim 1 in which the second semiconductor line comprises polysilicon.

Claim 9

The array of claim 1 in which the mth scan line comprises aluminum.

Claim 10

The array of claim 1 in which the first and second semiconductor lines are separated at the channel by an insulating layer; the insulating layer being an oxide.

Claim 11

The array of claim 1 in which the component comprises a capacitive element; the capacitive element comprising: a first electrode that is part of the (m+1)th scan line; a second electrode that is between the (m+1)th scan line and the substrate; the second electrode being connected to the data lead; and an insulating layer between the first and second electrodes; the first electrode extending between crossing regions in which the nth and (n+1)th data lines cross the (m+1)th scan line.

Claim 12

The array of claim 10 in which the first electrode has a first width in the second direction between first and second edges; the second electrode having a second width in the second direction between third and fourth edges; the first and second widths being approximately equal; the first and third edges being approximately aligned with each other and the second and fourth edges being approximately aligned with each other.

Claim 13

The array of claim 1 in which the mth and (m+1)th scan lines and the nth and (n+1)th data lines bound a cell area; the component comprising a cell electrode in the cell area; the cell electrode being connected to the data lead.

Claim 14

The array of claim 12 in which the cell electrode is light transmissive.

Claim 15

The array of claim 1 in which the nth data line has a width in the first direction between fifth and sixth edges; the first channel being between the fifth and sixth edges.

Claim 16

The array of claim 14 in which the first semiconductor line is between the nth data line and the substrate.

Claim 17

The array of claim 14 in which substantially all of the second semiconductor line is between the fifth and sixth edges; the second semiconductor line being connected to the mth scan line in the crossing region.

Claim 18

The array of claim 1 in which the first semiconductor line further includes a second channel in series with the first channel; the second semiconductor line further crossing the first semiconductor line at the second channel so that signals on the mth scan line also control conductivity of the second channel.

Claim 19

The array of claim 1 in which the set of one or more of the crossing regions includes all of the crossing regions.

Claim 20

The array of claim 1 in which the mth scan line's cross section is substantially uniform across the array.

Claim 21

A display comprising: a substrate with a surface at which circuitry can be formed; array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of M scan lines, where M is greater than 1; each of the scan lines extending approximately in a first direction across the surface of the substrate; the M scan lines being positioned in order from first through Mth; a set of N data lines, where N is greater than 1; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being perpendicular to the first direction; the N data lines being positioned in order from first through Nth; for each value of m from 1 through M and for each value of n from 1 through N, a crossing region in which the mth scan line and the nth data line cross; for each of a set of one or more of the crossing regions, cell circuitry connected to the mth scan line and the nth data line; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from the nth data line; the mth and (m+1)th scan lines and the nth and (n+1)th data lines bounding a cell area; the component comprising a light-transmissive cell electrode in the cell area; the cell electrode being connected for receiving signals from the data lead; connecting circuitry for electrically connecting the data lead to the nth data line under control of the mth scan line; the mth scan line comprising metal; the connecting circuitry comprising: a first semiconductor line connected between the nth data line and the data lead; the first semiconductor line including a first channel; and a second semiconductor line connected to the mth scan line and crossing the first semiconductor line at the first channel; the second semiconductor line being conductive; and a liquid crystal material positioned along the cell electrode so that signals on the mth scan line control light transmissivity of the liquid crystal material by controlling conductivity of the first channel.

Claim 22

A display comprising: a substrate with a surface at which circuitry can be formed; array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of M scan lines, where M is greater than 1; each of the scan lines extending approximately in a first direction across the surface of the substrate; the M scan lines being positioned in order from first through Mth; a set of N data lines, where N is greater than 1; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being perpendicular to the first direction; the N data lines being positioned in order from first through Nth; for each value of m from 1 through M and for each value of n from 1 through N, a crossing region in which the mth scan line and the nth data line cross; for each of a set of one or more of the crossing regions, cell circuitry connected to the mth scan line and the nth data line; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from the nth data line; the mth and (m+1)th scan lines and the nth and (n+1)th data lines bounding a cell area; the component comprising a light-transmissive cell electrode in the cell area; the cell electrode being connected for receiving signals from the data lead; connecting circuitry for electrically connecting the data lead to the nth data line under control of the mth scan line; the mth scan line comprising metal; the connecting circuitry comprising: a first semiconductor line connected between the nth data line and the data lead; the first semiconductor line including a first channel; and a second semiconductor line connected to the mth scan line and crossing the first semiconductor line at the first channel; the second semiconductor line being conductive; and a liquid crystal material positioned along the cell electrode so that signals on the mth scan line control light transmissivity of the liquid crystal material by controlling conductivity of the first channel.

Claim 23

The display of claim 20 in which the array circuitry has an outer boundary; the scan lines and the data lines extending across the outer boundary; the display further comprising: peripheral circuitry formed at the surface of the substrate outside the outer boundary of the array circuitry; the peripheral circuitry comprising: scan circuitry connected to the scan lines; and data circuitry connected to the data lines.

Claim 24

An array comprising: a substrate with a surface at which circuitry can be formed; and array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of two or more scan lines, each of the scan lines extending approximately in a first direction across the surface of the substrate; a set of two or more data lines; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being different than the first direction so that each of the scan lines and each of the data lines cross in a crossing region; for each of a set of one or more of the crossing regions, cell circuitry connected to the scan line and the data line that cross in the crossing region; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from or providing signals to the data line; and connecting circuitry for electrically connecting the data lead to the data line under control of the scan line; the scan line comprising metal; the connecting circuitry comprising: a first semiconductor line electrically connected between the data line and the data lead; and a second semiconductor line that crosses the first semiconductor line; the first semiconductor line including a channel where the second semiconductor line crosses it; the second semiconductor line being electrically connected to the scan line so that signals on the scan line control conductivity of the channel in the first semiconductor line.

Claim 25

An array comprising: a substrate with a surface at which circuitry can be formed; and array circuitry formed at the surface of the substrate, the array circuitry comprising: a set of two or more scan lines, each of the scan lines extending approximately in a first direction across the surface of the substrate; a set of two or more data lines; each of the data lines extending approximately in a second direction across the surface of the substrate; the second direction being different than the first direction so that each of the scan lines and each of the data lines cross in a crossing region; for each of a set of one or more of the crossing regions, cell circuitry connected to the scan line and the data line that cross in the crossing region; the cell circuitry of each crossing region in the set comprising: a component having a data lead for receiving signals from or providing signals to the data line; and connecting circuitry for electrically connecting the data lead to the data line under control of the scan line; the scan line comprising metal; the connecting circuitry comprising: a first semiconductor line electrically connected between the data line and the data lead; and a second semiconductor line that crosses the first semiconductor line; the first semiconductor line including a channel where the second semiconductor line crosses it; the second semiconductor line being electrically connected to the scan line so that signals on the scan line control conductivity of the channel in the first semiconductor line.

Claim 26

The array of claim 22 in which the second semiconductor line is conductive.