US5599424A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor devices
Assignee: Panasonic Holdings Corp
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Filing: 1995-12-13
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Granted: 1997-02-04
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Expires: 2015-12-13
Abstract
Abstract On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0 2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.
Inventors
- 👤 Shoji Matsumoto
- 👤 Yoshihisa Nagano
- 👤 Yasuhiro Shimada
- 👤 Yasufumi Izutsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:18
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
92 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulation layer, a first metal layer, a dielectric film, and a second metal layer on a substrate having circuit elements formed thereon; dry etching said second metal layer and said dielectric film to form a top electrode and a capacitance insulation film, wherein at least this dry etching step is performed using a gas containing hydrocarbon; and dry etching said first metal layer to form a bottom electrode after dry etching said second metal layer and said dielectric film.
Claim 2
Independent Claim
92 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulation layer, a first metal layer, a dielectric film, and a second metal layer on a substrate having circuit elements formed thereon; dry etching said second metal layer and said dielectric film to form a top electrode and a capacitance insulation film, wherein at least this dry etching step is performed using a gas containing hydrocarbon; and dry etching said first metal layer to form a bottom electrode after dry etching said second metal layer and said dielectric film.
Claim 3
Dependent Claim
18 words
A method of manufacturing a semiconductor device according to claim 1, wherein the gas containing hydrocarbon is chloroform.
Claim 4
Dependent Claim
26 words
A method of manufacturing a semiconductor device according to claim 1, wherein the gas containing hydrocarbon is a mixed gas of chloroform and Cl 2 gas.
Claim 5
Dependent Claim
24 words
A method of manufacturing a semiconductor device according to claim 1, wherein the gas containing hydrocarbon is a mixed gas of chloroform and HBr.
Claim 6
Dependent Claim
20 words
A method of manufacturing a semiconductor device according to claim 1, wherein the insulation layer is a silicon oxide layer.
Claim 7
Dependent Claim
27 words
A method of manufacturing a semiconductor device according to claim 1, wherein the first metal layer and the second metal layer are comprised of platinum or palladium.
Claim 8
Independent Claim
106 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulation layer, a first metal layer, a dielectric film, and a second metal layer on a substrate having circuit elements formed thereon; dry etching said second metal layer and said dielectric film to form a top electrode and a capacitance insulation film; and dry etching said first metal layer to form a bottom electrode after dry etching said second metal layer and said dielectric film, wherein dry etching of said first metal layer, said second metal layer, and said dielectric film is conducted in a low pressure region where etching speed is high.
Claim 9
Independent Claim
106 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulation layer, a first metal layer, a dielectric film, and a second metal layer on a substrate having circuit elements formed thereon; dry etching said second metal layer and said dielectric film to form a top electrode and a capacitance insulation film; and dry etching said first metal layer to form a bottom electrode after dry etching said second metal layer and said dielectric film, wherein dry etching of said first metal layer, said second metal layer, and said dielectric film is conducted in a low pressure region where etching speed is high.
Claim 10
Dependent Claim
22 words
A method of manufacturing a semiconductor device according to claim 7, wherein the low pressure region does not exceed about 5 Pa.
Claim 11
Independent Claim
141 words
A method for manufacturing a semiconductor device comprising the steps of: forming an insulation layer, a first metal layer, a dielectric film, and a second metal layer on a substrate having circuit elements formed thereon; dry etching said second metal layer and said dielectric film, in a low pressure region where etching speed is high, to form a top electrode and a capacitance insulation film; and etching off any remaining dielectric film left unetched on the first metal layer as soon as the first metal layer is exposed, said etching off being performed in a high pressure region where the etching speed of the first metal layer is slow; applying a mask pattern to the first metal layer; and dry etching the first metal layer in a low pressure region where the etching speed is high to form a bottom electrode.
Claim 12
Independent Claim
141 words
A method for manufacturing a semiconductor device comprising the steps of: forming an insulation layer, a first metal layer, a dielectric film, and a second metal layer on a substrate having circuit elements formed thereon; dry etching said second metal layer and said dielectric film, in a low pressure region where etching speed is high, to form a top electrode and a capacitance insulation film; and etching off any remaining dielectric film left unetched on the first metal layer as soon as the first metal layer is exposed, said etching off being performed in a high pressure region where the etching speed of the first metal layer is slow; applying a mask pattern to the first metal layer; and dry etching the first metal layer in a low pressure region where the etching speed is high to form a bottom electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |