Semiconductor memory

Claim 2

A semiconductor memory comprising: a memory portion having a plurality of memory cells furnished at the points of intersection between a plurality of word lines and a plurality of data lines; an operation circuit having a plurality of operation modes and operating in accordance with a designated operation mode; a first external terminal; a first output circuit furnished interposingly between the output terminal of said operation circuit and said first external terminal, said first output circuit feeding the output data of said operation circuit to said first external terminal; a second output circuit furnished interposingly between said output terminal of said operation circuit and said memory portion, said second output circuit feeding the output data of said operation circuit as write data to said memory portion; a first input circuit for providing a first input terminal of said operation circuit with first data supplied from outside said semiconductor memory; and a second input circuit furnished interposingly between a second input terminal of said operation circuit and said memory portion, said second input circuit providing said second input terminal with second data retrieved from said memory portion; wherein said operation circuit receives and operates on said first and said second data in accordance with said designated operation mode; and wherein the output data of said operation circuit is given to said first external terminal in the operation cycle in which the same output data is written to said memory portion.

Claim 3

A semiconductor memory according to claim 1, further comprising: a second external terminal for receiving a row address strobe signal /RAS; a third external terminal for receiving a column address strobe signal /CAS; a fourth external terminal for receiving a write enable signal /WE; a fifth external terminal for receiving a chip select signal /CS; and a control circuit connected to said second external terminal, said third external terminal, said fourth external terminal and said fifth external terminal, respectively, said control circuit outputting control signals upon detecting the levels of said row address strobe signal, said column address strobe signal, said write enable signal and said chip select signal received by said second, third, fourth and fifth external terminals, respectively; wherein the operation mode of said operation circuit is designated on the basis of said control signals.

Claim 4

A semiconductor memory according to claim 2, further comprising: a first switch circuit for selectively supplying said second output circuit with one of said output data of said operation circuit and said first data; a second switch circuit for selectively supplying said first output circuit with one of said output data of said operation circuit and said second data; and an external address terminal; wherein said first and said second switch circuit are controlled in accordance with the signal fed to said external address terminal.

Claim 5

A semiconductor memory according to claim 3, further comprising: a sixth external terminal; and a serial output circuit connected to said memory portion so as to store a parallel signal output from said memory portion and to output serially said parallel signal to said sixth external terminal.

Claim 6

A semiconductor memory according to claim 4, wherein said first data is obtained from said first external terminal.

Claim 7

A semiconductor memory according to claim 5, wherein said plurality of memory cells are dynamic memory cells.

Claim 8

A semiconductor memory according to claim 2, wherein the operation of said operation circuit is carried out, said output data of said operation circuit is written to said memory portion, and said output data of said operation circuit is fed to said first external terminal while said row address strobe signal /RAS is being driven Low continuously.

Claim 9

A semiconductor memory comprising: a first and a second memory array each having a plurality of memory cells furnished at the points of intersection between a plurality of word lines and a plurality of data lines; a first selection circuit for selecting memory cells of said first memory array; a second selection circuit for selecting memory cells of said second memory array; an operation circuit having a plurality of operation modes and operating in accordance with a designated operation mode; a first external terminal; a first output circuit furnished interposingly between the output terminal of said operation circuit and said first external terminal, said first output circuit feeding the output data of said operation circuit to said first external terminal; a second output circuit furnished interposingly between said output terminal of said operation circuit and said first memory array, said second output circuit feeding said output data of said operation circuit to said first memory array as write data; a third output circuit furnished interposingly between said output terminal of said operation circuit and said second memory array, said third output circuit feeding said output data of said operation circuit to said second memory array as write data; a first input circuit for providing a first input terminal of said operation circuit with first data supplied from outside said semiconductor memory; and a second input circuit for providing a second input terminal of said operation circuit with second data retrieved either from said first memory array or from said second memory array; wherein said operation circuit receives and operates on said first and said second data in accordance with said designated operation mode; and wherein the output data of said operation circuit is given to said first external terminal in the operation cycle in which the same output data is written to memory cells either of said first memory array or of said second memory array.

Claim 10

A semiconductor memory comprising: a first and a second memory array each having a plurality of memory cells furnished at the points of intersection between a plurality of word lines and a plurality of data lines; a first selection circuit for selecting memory cells of said first memory array; a second selection circuit for selecting memory cells of said second memory array; an operation circuit having a plurality of operation modes and operating in accordance with a designated operation mode; a first external terminal; a first output circuit furnished interposingly between the output terminal of said operation circuit and said first external terminal, said first output circuit feeding the output data of said operation circuit to said first external terminal; a second output circuit furnished interposingly between said output terminal of said operation circuit and said first memory array, said second output circuit feeding said output data of said operation circuit to said first memory array as write data; a third output circuit furnished interposingly between said output terminal of said operation circuit and said second memory array, said third output circuit feeding said output data of said operation circuit to said second memory array as write data; a first input circuit for providing a first input terminal of said operation circuit with first data supplied from outside said semiconductor memory; and a second input circuit for providing a second input terminal of said operation circuit with second data retrieved either from said first memory array or from said second memory array; wherein said operation circuit receives and operates on said first and said second data in accordance with said designated operation mode; and wherein the output data of said operation circuit is given to said first external terminal in the operation cycle in which the same output data is written to memory cells either of said first memory array or of said second memory array.

Claim 11

A semiconductor memory according to claim 8, further comprising: a second external terminal for receiving a row address strobe signal /RAS; a third external terminal for receiving a column address strobe signal /CAS; a fourth external terminal for receiving a write enable signal /WE; a fifth external terminal for receiving a chip select signal /CS; and a control circuit having a first input connected to said second external terminal, a second input connected to said third external terminal, a third input connected to said fourth external terminal and a fourth input connected to said fifth external terminal, said control circuit outputting control signals upon detecting the levels of said row address strobe signal, said column address strobe signal, said write enable signal and said chip select signal received by said second, third, fourth and fifth external terminals, respectively; wherein the operation mode of said operation circuit is designated in accordance with the control signals output by said control circuit.

Claim 12

A semiconductor memory according to claim 9, wherein the operation of said operation circuit is carried out, said output data of said operation circuit is written either to said first memory array or to said second memory array, and said output data of said operation circuit is fed to said first external terminal while said row address strobe signal /RAS is being driven Low continuously.

Claim 13

A semiconductor memory comprising: a memory portion having a plurality of memory cells furnished at the points of intersection between a plurality of word lines and a plurality of data lines; an operation circuit having a plurality of operation modes and operating in accordance with a designated operation mode; a selection circuit furnished interposingly between the output terminal of said operation circuit and said memory portion, said selection circuit selecting memory cells in said memory portion in accordance with the address signal output by said operation circuit; a first input circuit for providing a first input terminal of said operation circuit with a first address signal supplied from outside said semiconductor memory; and a second input circuit furnished interposingly between a second input terminal of said operation circuit and said memory portion, said second input circuit providing said second input terminal with a second address signal retrieved from said memory portion; wherein said operation circuit receives and operates on said first and said second address signal in accordance with said designated operation mode.

Claim 14

A semiconductor memory comprising: a memory portion having a plurality of memory cells furnished at the points of intersection between a plurality of word lines and a plurality of data lines; an operation circuit having a plurality of operation modes and operating in accordance with a designated operation mode; a selection circuit furnished interposingly between the output terminal of said operation circuit and said memory portion, said selection circuit selecting memory cells in said memory portion in accordance with the address signal output by said operation circuit; a first input circuit for providing a first input terminal of said operation circuit with a first address signal supplied from outside said semiconductor memory; and a second input circuit furnished interposingly between a second input terminal of said operation circuit and said memory portion, said second input circuit providing said second input terminal with a second address signal retrieved from said memory portion; wherein said operation circuit receives and operates on said first and said second address signal in accordance with said designated operation mode.

Claim 15

A semiconductor memory according to claim 11, further comprising: a first external terminal for receiving a row address strobe signal /RAS; a second external terminal for receiving a column address strobe signal /CAS; a third external terminal for receiving a write enable signal /WE; a fourth external terminal for receiving a chip select signal /CS; and a control circuit having a first input connected to said second external terminal, a second input connected to said third external terminal, a third input connected to said fourth external terminal and a fourth input connected to said fifth external terminal, said control circuit outputting control signals upon detecting the levels of said row address strobe signal, said column address strobe signal, said write enable signal and said chip select signal received by said second, third, fourth and fifth external terminals, respectively; wherein the operation mode of said operation circuit is designated on the basis of said control signals.