US5598348A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for analyzing the power network of a VLSI circuit
Assignee: Sun Microsystems Inc
•
Filing: 1994-09-22
•
Granted: 1997-01-28
•
Expires: 2014-09-22
Abstract
Abstract A method and apparatus to model the power network of a VLSI circuit is described. The method includes the step of extracting the power network associated with a semiconductor circuit layout. A compacted power network is then derived from the power network. The compacted power network includes a compacted primary resistive network to characterize the electrical resistance of the power trunks within the semiconductor circuit layout. The compacted power network also includes a compacted secondary resistive network to characterize the electrical resistance of power straps that deliver power to transistors within the semiconductor circuit layout. The compacted power network constitutes a network of compaction component values that correspond to functional regions in the semiconductor circuit layout. Each of the compaction component values includes an associated set of spacial compaction values that characterize the total resistance of a functional region. The operation of the compacted power network is simulated on a circuit simulation program to identify areas in the compacted power network that do not comply with predetermined power network performance criteria, such as electromigration limits and voltage drop limits. The semiconductor circuit layout is then reconfigured to satisfy the predetermined power network performance criteria.
Inventors
- 👤 Stefan Rusu
- 👤 Clayton L. Yee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:09
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398; G06F30/36; G06F30/367
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
222 words
A method of analyzing the power network performance of a semiconductor circuit layout, said method comprising the steps of: extracting from a semiconductor circuit layout the power network associated with said semiconductor circuit layout; deriving a compacted resistive network corresponding to said power network, said deriving step including the steps of deriving a primary resistive network including a set of primary compaction components characterizing power trunks within said semiconductor circuit layout, each of said primary compaction components including an associated power trunk length value and power trunk width value for use in calculating a primary compaction component resistance value, and deriving a secondary resistive network including a set of secondary compaction components characterizing the electrical resistance of power straps that deliver power to transistors within said semiconductor circuit layout, each of said secondary compaction components including an associated power strap length value characterizing the physical length of the power straps in a functional region of said semiconductor circuit layout and a width value characterizing the physical width of the sum of all power straps in said functional region; running a circuit simulation of said compacted resistive network to identify any power network performance that does not comply with predetermined criteria; and refining the topology of said semiconductor circuit layout to improve power network performance that does not comply with said predetermined criteria.
Claim 2
Independent Claim
222 words
A method of analyzing the power network performance of a semiconductor circuit layout, said method comprising the steps of: extracting from a semiconductor circuit layout the power network associated with said semiconductor circuit layout; deriving a compacted resistive network corresponding to said power network, said deriving step including the steps of deriving a primary resistive network including a set of primary compaction components characterizing power trunks within said semiconductor circuit layout, each of said primary compaction components including an associated power trunk length value and power trunk width value for use in calculating a primary compaction component resistance value, and deriving a secondary resistive network including a set of secondary compaction components characterizing the electrical resistance of power straps that deliver power to transistors within said semiconductor circuit layout, each of said secondary compaction components including an associated power strap length value characterizing the physical length of the power straps in a functional region of said semiconductor circuit layout and a width value characterizing the physical width of the sum of all power straps in said functional region; running a circuit simulation of said compacted resistive network to identify any power network performance that does not comply with predetermined criteria; and refining the topology of said semiconductor circuit layout to improve power network performance that does not comply with said predetermined criteria.
Claim 3
Dependent Claim
48 words
The method of claim 1 further comprising the steps of: establishing a package resistive network to characterize the resistance of a package housing a semiconductor circuit corresponding to said semiconductor circuit layout; and combining said package resistive network into said compacted resistive network prior to said running step.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein said running step includes the step of identifying electromigration values that exceed a predetermined threshold value.
Claim 5
Dependent Claim
23 words
The method of claim 1 wherein said running step includes the step of identifying voltage drop values that exceed a predetermined threshold value.
Claim 6
Dependent Claim
254 words
A computer readable memory storing executable instructions for execution by a computer, comprising: a plurality of instruction sets stored in said computer readable memory, including a first instruction set to extract from a semiconductor circuit layout the power network associated with said semiconductor circuit layout; a second instruction set to derive a compacted resistive network corresponding to said power network, said second instruction set including first sub-set instruction to derive a primary resistive network including a set of primary compaction components characterizing power trunks within said semiconductor circuit layout, each of said primary compaction components including an associated power trunk length value and power trunk width value for use in calculating a primary compaction component resistance value, and second sub-set instructions to derive a secondary resistive network including a set of secondary compaction components characterizing the electrical resistance of power straps that deliver power to transistors within said semiconductor circuit layout, each of said secondary compaction components including an associated power strap length value characterizing the physical length of the power straps in a functional region of said semiconductor circuit layout and a width value characterizing the physical width of the sum of all power straps in said functional region; a third instruction set to run a circuit simulation of said compacted resistive network to identify any power network performance that does not comply with predetermined criteria; and a fourth instruction set to refine the topology of said semiconductor circuit layout to improve power network performance that does not comply with said predetermined criteria.
Claim 7
Dependent Claim
254 words
A computer readable memory storing executable instructions for execution by a computer, comprising: a plurality of instruction sets stored in said computer readable memory, including a first instruction set to extract from a semiconductor circuit layout the power network associated with said semiconductor circuit layout; a second instruction set to derive a compacted resistive network corresponding to said power network, said second instruction set including first sub-set instruction to derive a primary resistive network including a set of primary compaction components characterizing power trunks within said semiconductor circuit layout, each of said primary compaction components including an associated power trunk length value and power trunk width value for use in calculating a primary compaction component resistance value, and second sub-set instructions to derive a secondary resistive network including a set of secondary compaction components characterizing the electrical resistance of power straps that deliver power to transistors within said semiconductor circuit layout, each of said secondary compaction components including an associated power strap length value characterizing the physical length of the power straps in a functional region of said semiconductor circuit layout and a width value characterizing the physical width of the sum of all power straps in said functional region; a third instruction set to run a circuit simulation of said compacted resistive network to identify any power network performance that does not comply with predetermined criteria; and a fourth instruction set to refine the topology of said semiconductor circuit layout to improve power network performance that does not comply with said predetermined criteria.
Claim 8
Dependent Claim
60 words
The computer readable memory of claim 5 further including third sub-set instructions of said second instruction set to establish a package resistive network to characterize the resistance of a package housing a semiconductor circuit corresponding to said semiconductor circuit layout; and fourth sub-set instructions of said second instruction set to combine said package resistive network into said compacted resistive network.
Claim 9
Dependent Claim
23 words
The computer readable memory of claim 6 wherein said third instruction set includes instructions to identify electromigration values exceeding a predetermined threshold value.
Claim 10
Dependent Claim
22 words
The computer readable memory of claim 6 wherein said third instruction set includes instructions to identify voltage drops exceeding a predetermined threshold.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |