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US5598009A Expired / Lapsed US ⏱️ 0.0 years remaining

Hot carrier injection test structure and testing technique for statistical evaluation

Assignee: Advanced Micro Devices Inc
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Filing: 1995-06-06
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Granted: 1997-01-28
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Expires: 2015-06-06
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Abstract

Abstract An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area A g connected to a pad of area A p . In accordance with the present teachings, the antenna ratio R of the area of the pad A p to the area of the gate A g is a predetermined number. In practice, the ratio R would be chosen to be a minimum so that deleterious plasma currents attracted to the gate area would be reduced. In a particular implementation, the transistor includes plural gates each having a layer of at least partially conductive material of area A gn where n is any integer between 1 and N and where N is the total number of gates. In this case, the plural gates are interconnected and the ratio R is a predetermined number equal to A p /A gtotal , where A gtotal is the sum of the areas A gn and n is any integer between 1 and N. The novel method for testing multiple gate transistors includes the steps of connecting a first terminal of each of said transistors to a ground; interconnecting a second terminal of each transistor and applying a first source of supply potential; and selectively applying a second source of supply potential to a third terminal of a selected transistor.

Inventors

  • 👤 Nguyen D. Bui

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 16:29
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H10W; H10W72/00; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/981; H10W72/983

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 57 words
An improved method for testing multiple gate transistors including the steps of: connecting a source terminal of each of said transistors to a first ground; interconnecting a gate terminal of each transistor while applying a first source of supply potential; and selectively applying a second source of supply potential to a third terminal of a selected transistor.
Claim 2
Dependent Claim 57 words
An improved method for testing multiple gate transistors including the steps of: connecting a source terminal of each of said transistors to a first ground; interconnecting a gate terminal of each transistor while applying a first source of supply potential; and selectively applying a second source of supply potential to a third terminal of a selected transistor.

References Cited (Backward Citations)

US4075653A Cited
US5250835A Cited
JPH0637186A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-01-28 2000-07-29 2001-01-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-01-28 2004-07-29 2005-01-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-01-28 2008-07-29 2009-01-28 $7700.00 Window Closed / Lapsed

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