Method for manufacturing LDD type semiconductor device with complete self-alignment

Claim 1

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming an insulating layer on a semiconductor substrate of a first conductivity type; forming an opening in said insulating layer; forming a first sidewall insulating layer on a sidewall of said insulating layer within said opening; forming a gate insulating layer on said semiconductor substrate within said opening; forming a gate electrode buried in said opening on said first sidewall insulating layer and said gate insulating layer; removing said first sidewall insulating layer after formation of said gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said gate electrode and said insulating layer to form a first impurity region of said second conductivity type in said semiconductor substrate; removing said insulating layer after formation of said first impurity region; forming a second sidewall insulating layer on a sidewall of said gate electrode after removal of said insulating layer; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said gate electrode and said second sidewall insulating layer to form a second impurity region of said second conductivity type in said semiconductor substrate, said second impurity region having a higher impurity concentration than said first impurity region.

Claim 2

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming an insulating layer on a semiconductor substrate of a first conductivity type; forming an opening in said insulating layer; forming a first sidewall insulating layer on a sidewall of said insulating layer within said opening; forming a gate insulating layer on said semiconductor substrate within said opening; forming a gate electrode buried in said opening on said first sidewall insulating layer and said gate insulating layer; removing said first sidewall insulating layer after formation of said gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said gate electrode and said insulating layer to form a first impurity region of said second conductivity type in said semiconductor substrate; removing said insulating layer after formation of said first impurity region; forming a second sidewall insulating layer on a sidewall of said gate electrode after removal of said insulating layer; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said gate electrode and said second sidewall insulating layer to form a second impurity region of said second conductivity type in said semiconductor substrate, said second impurity region having a higher impurity concentration than said first impurity region.

Claim 6

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming an insulating layer on a semiconductor substrate of a first conductivity type; forming an opening in said insulating layer; forming a first sidewall insulating layer on a sidewall of said insulating layer within said opening; introducing impurities of said first conductivity type into said semiconductor substrate with a mask of said first sidewall insulating layer and said insulating layer to form a first impurity region of said first conductivity type in said semiconductor substrate; forming a gate insulating layer on said semiconductor substrate within said opening; forming a gate electrode buried in said opening on said first sidewall insulating layer and said gate insulating layer; removing said first sidewall insulating layer after formation of said gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said gate electrode and said insulating layer to form a second impurity region of said second conductivity type in said semiconductor substrate; removing said insulating layer after formation of said second impurity region; reducing said gate electrode in size after removal of said insulating layer; introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said reduced gate electrode to form a third impurity region of said second conductivity type, said third impurity region having a lower impurity concentration than said second impurity region; forming a second sidewall insulating layer on a sidewall of said gate electrode after formation of said third impurity region; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said gate electrode and said second sidewall insulating layer to form a fourth impurity region of said second conductivity type in said semiconductor substrate, said fourth impurity region having a higher impurity concentration than said second impurity region.

Claim 7

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming an insulating layer on a semiconductor substrate of a first conductivity type; forming an opening in said insulating layer; forming a first sidewall insulating layer on a sidewall of said insulating layer within said opening; introducing impurities of said first conductivity type into said semiconductor substrate with a mask of said first sidewall insulating layer and said insulating layer to form a first impurity region of said first conductivity type in said semiconductor substrate; forming a gate insulating layer on said semiconductor substrate within said opening; forming a gate electrode buried in said opening on said first sidewall insulating layer and said gate insulating layer; removing said first sidewall insulating layer after formation of said gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said gate electrode and said insulating layer to form a second impurity region of said second conductivity type in said semiconductor substrate; removing said insulating layer after formation of said second impurity region; reducing said gate electrode in size after removal of said insulating layer; introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said reduced gate electrode to form a third impurity region of said second conductivity type, said third impurity region having a lower impurity concentration than said second impurity region; forming a second sidewall insulating layer on a sidewall of said gate electrode after formation of said third impurity region; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said gate electrode and said second sidewall insulating layer to form a fourth impurity region of said second conductivity type in said semiconductor substrate, said fourth impurity region having a higher impurity concentration than said second impurity region.

Claim 8

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming a first silicon oxide layer on a semiconductor substrate of a first conductivity type; forming a polycrystalline silicon layer on said first silicon oxide layer; forming a second silicon oxide layer on said polycrystalline silicon layer; etching said second silicon oxide layer by using said polycrystalline silicon layer as an etching stopper to form an opening in said second silicon oxide layer; etching said polycrystalline silicon layer by using said first silicon oxide layer as an etching stopper with a mask of said second silicon oxide layer; forming a silicon nitride layer on said first and second silicon oxide layers after etching said polycrystalline silicon layer; etching back said silicon nitride layer to form a first sidewall layer on a sidewall of said second silicon oxide layer and said polycrystalline silicon layer; removing said first silicon oxide layer in said opening and forming a third silicon oxide layer on said semiconductor substrate; introducing impurities of said second conductivity type via said third silicon oxide layer into said semiconductor substrate; removing said third silicon oxide layer and forming a gate oxide layer on said semiconductor substrate; forming a gate electrode on said gate silicon oxide layer and surrounded by said first sidewall layer; removing said first sidewall layer surrounding said gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said gate electrode and said second silicon oxide layer to form a second impurity region of said conductivity type; removing said second silicon oxide layer and said polycrystalline silicon layer after formation of said second impurity region; forming a second sidewall layer on a sidewall of said gate electrode after removal of said second silicon oxide layer and said polycrystalline silicon layer; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said gate electrode and said second sidewall layer to form a third impurity region of said second conductivity type, said third impurity region having a higher impurity concentration than said second impurity region.

Claim 9

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming a first silicon oxide layer on a semiconductor substrate of a first conductivity type; forming a polycrystalline silicon layer on said first silicon oxide layer; forming a second silicon oxide layer on said polycrystalline silicon layer; etching said second silicon oxide layer by using said polycrystalline silicon layer as an etching stopper to form an opening in said second silicon oxide layer; etching said polycrystalline silicon layer by using said first silicon oxide layer as an etching stopper with a mask of said second silicon oxide layer; forming a silicon nitride layer on said first and second silicon oxide layers after etching said polycrystalline silicon layer; etching back said silicon nitride layer to form a first sidewall layer on a sidewall of said second silicon oxide layer and said polycrystalline silicon layer; removing said first silicon oxide layer in said opening and forming a third silicon oxide layer on said semiconductor substrate; introducing impurities of said second conductivity type via said third silicon oxide layer into said semiconductor substrate; removing said third silicon oxide layer and forming a gate oxide layer on said semiconductor substrate; forming a gate electrode on said gate silicon oxide layer and surrounded by said first sidewall layer; removing said first sidewall layer surrounding said gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said gate electrode and said second silicon oxide layer to form a second impurity region of said conductivity type; removing said second silicon oxide layer and said polycrystalline silicon layer after formation of said second impurity region; forming a second sidewall layer on a sidewall of said gate electrode after removal of said second silicon oxide layer and said polycrystalline silicon layer; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said gate electrode and said second sidewall layer to form a third impurity region of said second conductivity type, said third impurity region having a higher impurity concentration than said second impurity region.

Claim 13

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming a first silicon oxide layer on a semiconductor substrate of a first conductivity type; forming a polycrystalline silicon layer on said first silicon oxide layer; forming a second silicon oxide layer on said polycrystalline silicon layer; etching said second silicon oxide layer by using said polycrystalline silicon layer as an etching stopper to form an opening in said second silicon oxide layer; etching said polycrystalline silicon layer by using said first silicon oxide layer as an etching stopper with a mask of said second silicon oxide layer; forming a silicon nitride layer on said first and second silicon oxide layers after etching said polycrystalline silicon layer; etching back said silicon nitride layer to form a first sidewall layer on a sidewall of said second silicon oxide layer and said polycrystalline silicon layer; removing said first silicon oxide layer in said opening and forming a third silicon oxide layer on said semiconductor substrate; introducing impurities of said second conductivity type via said third silicon oxide layer into said semiconductor substrate; removing said third silicon oxide layer and forming a gate oxide layer on said semiconductor substrate; forming a polycrystalline silicon gate electrode on said gate silicon oxide layer and surrounded by said first sidewall layer; removing said first sidewall layer surrounding said polycrystalline silicon gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said polycrystalline silicon gate electrode and said second silicon oxide layer to form a second impurity region of said conductivity type; removing said second silicon oxide layer and said polycrystalline silicon layer after formation of said second impurity region; thermally oxidizing said polycrystalline silicon gate electrode after removal of said second silicon oxide layer and said polycrystalline silicon layer, to form a fourth silicon oxide layer on said polycrystalline silicon gate electrode; removing said fourth silicon oxide layer; forming a second sidewall layer on a sidewall of said polycrystalline silicon gate electrode after removal of said fourth silicon oxide layer; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said polycrystalline silicon gate electrode and said second sidewall layer to form a third impurity region of said second conductivity type, said third impurity region having a higher impurity concentration than said second impurity region.

Claim 14

A method for manufacturing a lightly-doped drain (LDD)-type semiconductor device, comprising the steps of: forming a first silicon oxide layer on a semiconductor substrate of a first conductivity type; forming a polycrystalline silicon layer on said first silicon oxide layer; forming a second silicon oxide layer on said polycrystalline silicon layer; etching said second silicon oxide layer by using said polycrystalline silicon layer as an etching stopper to form an opening in said second silicon oxide layer; etching said polycrystalline silicon layer by using said first silicon oxide layer as an etching stopper with a mask of said second silicon oxide layer; forming a silicon nitride layer on said first and second silicon oxide layers after etching said polycrystalline silicon layer; etching back said silicon nitride layer to form a first sidewall layer on a sidewall of said second silicon oxide layer and said polycrystalline silicon layer; removing said first silicon oxide layer in said opening and forming a third silicon oxide layer on said semiconductor substrate; introducing impurities of said second conductivity type via said third silicon oxide layer into said semiconductor substrate; removing said third silicon oxide layer and forming a gate oxide layer on said semiconductor substrate; forming a polycrystalline silicon gate electrode on said gate silicon oxide layer and surrounded by said first sidewall layer; removing said first sidewall layer surrounding said polycrystalline silicon gate electrode; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said polycrystalline silicon gate electrode and said second silicon oxide layer to form a second impurity region of said conductivity type; removing said second silicon oxide layer and said polycrystalline silicon layer after formation of said second impurity region; thermally oxidizing said polycrystalline silicon gate electrode after removal of said second silicon oxide layer and said polycrystalline silicon layer, to form a fourth silicon oxide layer on said polycrystalline silicon gate electrode; removing said fourth silicon oxide layer; forming a second sidewall layer on a sidewall of said polycrystalline silicon gate electrode after removal of said fourth silicon oxide layer; and introducing impurities of said second conductivity type into said semiconductor substrate with a mask of said polycrystalline silicon gate electrode and said second sidewall layer to form a third impurity region of said second conductivity type, said third impurity region having a higher impurity concentration than said second impurity region.