Patent US5596759A successfully refreshed from Google Patents.
US5596759A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for initializing a multiple processor computer system using a common ROM
Assignee: HP Inc
•
Filing: 1995-10-03
•
Granted: 1997-01-21
•
Expires: 2015-10-03
Abstract
Abstract Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
Inventors
- 👤 David A. Miller
- 👤 Kenneth A. Jansen
- 👤 Montgomery C. McGraw
- 👤 Darren J. Cepulis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:43
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1417; G06F11/22; G06F11/2284; G06F15/00; G06F15/16; G06F15/177; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4403; G06F9/4405; G06F11/16; G06F11/20; G06F11/202; G06F11/2038; G06F11/2043; G06F9/4416
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
122 words
A method of initializing a multi-processor computer system, the multi-processor computer system including at least two processors, one of which is considered a primary processor during initialization, said processors being powered up together; common peripherals; and a common storage element which stores initialization code used during start up of the computer system, the common storage element being common to each processor, the initialization code having processor and common peripheral portions, the method comprising the steps of: (a) each processor executing initialization code stored in the common storage element; (b) each processor performing processor initialization code to initialize itself; and (c) each processor determining if it is the primary processor and performing common peripheral initialization code only if it is said primary processor.
Claim 2
Independent Claim
122 words
A method of initializing a multi-processor computer system, the multi-processor computer system including at least two processors, one of which is considered a primary processor during initialization, said processors being powered up together; common peripherals; and a common storage element which stores initialization code used during start up of the computer system, the common storage element being common to each processor, the initialization code having processor and common peripheral portions, the method comprising the steps of: (a) each processor executing initialization code stored in the common storage element; (b) each processor performing processor initialization code to initialize itself; and (c) each processor determining if it is the primary processor and performing common peripheral initialization code only if it is said primary processor.
Claim 3
Dependent Claim
18 words
The method of claim 1, wherein each processor executes said initialization code directly from the common storage element.
Claim 4
Dependent Claim
95 words
The method of claim 1, wherein the multi-processor computer system further includes an active processor identifying value indicating a reset condition, the method further including the steps of: (d) each processor acquiring the active processor identifying value; and (e) each processor selecting a portion of said initialization code to execute based on the active processor identifying value, wherein each processor is identified as a primary or secondary processor, and wherein each processor identified as a primary processor initializes the common peripherals and each processor identified as a secondary processor does not initialize the common peripherals.
Claim 5
Dependent Claim
26 words
The method of claim 1, wherein the active processor identifying value is acquired from an identification register having bits reflecting the active state of the processors.
Claim 6
Dependent Claim
137 words
The method of claim 1, wherein the multi-processor computer system further includes a non-volatile programmable memory for holding a reset code indicating a reset condition, the reset code being in a normal condition after the system reset, the method further including the steps of: (f) each processor reading the reset code from said non-volatile programmable memory after release of the system reset; and (g) each processor selecting a portion of said initialization code to execute based on the reset code, wherein each processor deems itself to be said primary processor and initializes the common peripherals if the reset code indicates a normal type of reset condition present and each processor deems itself to be a secondary processor and does not initialize the common peripherals if the reset code does not indicate a normal type of reset condition.
Claim 7
Dependent Claim
50 words
The method of claim 1, further comprising the steps of: (h) applying and releasing a system reset to the multi-processor computer system before steps (a)-(c), the system reset causing all but one of said processors to be restrained; and (i) said primary processor causing each other processor to be released.
Claim 8
Dependent Claim
91 words
The method of claim 6, wherein the multi-processor computer system further includes an active processor identifying value, the method further including the steps of: (j) each processor acquiring the active processor identifying value; and (k) each processor selecting a portion of said initialization code to execute based on the active processor identifying value, wherein each processor is identified as a primary or secondary processor, and wherein each processor identified as a primary processor initializes the common peripherals and each processor identified as a secondary processor does not initialize the common peripherals.
Claim 9
Dependent Claim
82 words
The method of claim 6, wherein the multi-processor computer system further includes a main memory for storing redirection vectors and wherein step (i) further comprises the steps of: (l) said primary processor writing an address into a redirection vector location of main memory, said address pointing to a starting address of a portion of said initialization code not causing the common peripherals to be initialized; and (m) said primary processor causing each other processor to be released after setting the redirection vector.
Claim 10
Dependent Claim
137 words
The method of claim 6, wherein said multi-processor computer system further includes a non-volatile programmable memory for holding a reset code indicating a reset condition, the reset code being in a normal condition after the system reset, the method further including the steps of: (n) each processor reading the reset code from the non-volatile programmable memory after release of the system reset; and (o) each processor selecting a portion of said initialization code to execute based on the reset code, wherein each processor deems itself to be said primary processor and initializes the common peripherals if the reset code indicates a normal type of reset condition present and each processor deems itself to be a secondary processor and does not initialize the common peripherals if the reset code does not indicate a normal type of reset condition.
Claim 11
Dependent Claim
81 words
The method of claim 9 wherein the multi-processor computer system further includes a main memory for storing redirection vectors, wherein step (i) further comprises the steps of: (p) said primary processor writing an address into a redirection vector location of main memory, said address pointing to a starting address of a portion of said initialization code not causing the common peripherals to be initializated; and (q) said primary processor causing each other processor to be released after setting the redirection vector.
Claim 12
Dependent Claim
133 words
A multiprocessor computer system, comprising: at least two processors, one of which is considered a primary processor during initialization, said processors being powered up together; a common storage element containing processor executable initialization code used during start-up of the computer system, the common storage element being common to each processor, said initialization code having processor and common peripheral initialization code; a common peripheral including a hard disk; wherein said initialization code when executed by said processors causes said processors to perform the steps of: (a) each processor executing said initialization code stored in the common storage element; (b) each processor performing said processor initialization code to initialize itself; and (c) each processor determining if it is the primary processor and performing said common peripheral initialization code only if it is said primary processor.
Claim 13
Dependent Claim
133 words
A multiprocessor computer system, comprising: at least two processors, one of which is considered a primary processor during initialization, said processors being powered up together; a common storage element containing processor executable initialization code used during start-up of the computer system, the common storage element being common to each processor, said initialization code having processor and common peripheral initialization code; a common peripheral including a hard disk; wherein said initialization code when executed by said processors causes said processors to perform the steps of: (a) each processor executing said initialization code stored in the common storage element; (b) each processor performing said processor initialization code to initialize itself; and (c) each processor determining if it is the primary processor and performing said common peripheral initialization code only if it is said primary processor.
Claim 14
Dependent Claim
20 words
The multiprocessor computer system of claim 11, wherein each processor executes said initialization code directly from the common storage element.
Claim 15
Dependent Claim
105 words
The multiprocessor computer system of claim 11, wherein the multi-processor computer system further includes an active processor identifying value and wherein said initialization code when executed by said processors causes said processors to further perform the steps of: (d) each processor acquiring the active processor identifying value; and (e) each processor selecting a portion of said initialization code to execute based on the active processor identifying value, wherein each processor is identified as a primary or secondary processor, and wherein each processor identified as a primary processor initializes the common peripherals and each processor identified as a secondary processor does not initialize the common peripherals.
Claim 16
Dependent Claim
28 words
The multiprocessor computer system of claim 11, wherein the active processor identifying value is acquired from an identification register having bits reflecting the active state of the processors.
Claim 17
Dependent Claim
151 words
The multiprocessor computer system of claim 11, wherein the multi-processor computer system further includes a non-volatile programmable memory for holding a reset code indicating a reset condition, the reset code being in a normal condition after the system reset, and wherein said initialization code when executed by said processors causes said processors to further perform the steps of: (f) each processor reading the reset code from said non-volatile programmable memory after release of the system reset; and (g) each processor selecting a portion of said initialization code to execute based on the reset code, wherein each processor deems itself to be said primary processor and initializes the common peripherals if the reset code indicates a normal type of reset condition present and each processor deems itself to be a secondary processor and does not initialize the common peripherals if the reset code does not indicate a normal type of reset condition.
Claim 18
Dependent Claim
65 words
The multiprocessor computer system of claim 11, wherein said initialization code when executed by said processors causes said processors to further perform the steps of: (h) applying and releasing a system reset to the multi-processor computer system before steps (a)-(c), the system reset causing all but one of said processors to be restrained; and (i) said primary processor causing each other processor to be released.
Claim 19
Dependent Claim
106 words
The multiprocessor computer system of claim 16, wherein the multi-processor computer system further includes an active processor identifying value and wherein said initialization code when executed by said processors causes said processors to further perform the steps of: (j) each processor acquiring the active processor identifying value; and (k) each processor selecting a portion of said initialization code to execute based on the active processor identifying value, wherein each processor is identified as a primary or secondary processor, and wherein each processor identified as a said primary processor initializes the common peripherals and each processor identified as a secondary processor does not initialize the common peripherals.
Claim 20
Dependent Claim
97 words
The multiprocessor computer system of claim 16, wherein the multi-processor computer system further includes a main memory for storing redirection vectors and wherein step (i) of said initialization code when executed by said processors causes said processors to further perform the steps of: (l) said primary processor writing an address into a redirection vector location of main memory, said address pointing to a starting address of a portion of said initialization code not causing the common peripherals to be initialized; and (m) said primary processor causing each other processor to be released after setting the redirection vector.
Claim 21
Dependent Claim
151 words
The multiprocessor computer system of claim 16, wherein said multi-processor computer system further includes a non-volatile programmable memory for holding a reset code indicating a reset condition, the reset code being in a normal condition after the system reset, and wherein said initialization code when executed by said processors causes said processors to further perform the steps of: (n) each processor reading the reset code from the non-volatile programmable memory after release of the system reset; and (o) each processor selecting a portion of said initialization code to execute based on the reset code, wherein each processor deems itself to be said primary processor and initializes the common peripherals if the reset code indicates a normal type of reset condition present and each processor deems itself to be a secondary processor and does not initialize the common peripherals if the reset code does not indicate a normal type of reset condition.
Claim 22
Dependent Claim
97 words
The multiprocessor computer system of claim 19 wherein the multi-processor computer system further includes a main memory for storing redirection vectors and wherein step (i) of said initialization code when executed by said processors causes said processors to further perform the steps of: (p) said primary processor writing an address into a redirection vector location of main memory, said address pointing to a starting address of a portion of said initialization code not causing the common peripherals to be initializated; and (q) said primary processor causing each other processor to be released after setting the redirection vector.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |