Patent US5596534A successfully refreshed from Google Patents.
US5596534A
Expired / Lapsed
US
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Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM
Assignee: Micron Technology Inc
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Filing: 1995-06-27
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Granted: 1997-01-21
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Expires: 2015-06-27
Abstract
Abstract An integrated circuit comprising a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed or refreshed in response to a first signal; and a timing circuit which engages the filter in response to presence of a first signal, and causes the filter to filter the reference voltage. A method of increasing the speed of operation of an integrated circuit including a dynamic random access memory having memory cells which are individually accessed in response to a signal, including a reference voltage generator having an output, and including a voltage regulator which accepts the output of the reference voltage generator and supplies voltage to the dynamic random access memory, the method comprising filtering the output of the reference voltage generator in response to the signal.
Inventors
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:02
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
108 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed or refreshed in response to a first signal; and a timing circuit which engages the filter in response to the first signal, and causes the filter to filter the reference voltage.
Claim 2
Dependent Claim
108 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed or refreshed in response to a first signal; and a timing circuit which engages the filter in response to the first signal, and causes the filter to filter the reference voltage.
Claim 3
Dependent Claim
16 words
An integrated circuit in accordance with claim 1 wherein the filter is a low pass filter.
Claim 4
Dependent Claim
20 words
An integrated circuit in accordance with claim 1 wherein the filter comprises a low pass filter including a resistor-capacitor network.
Claim 5
Dependent Claim
36 words
An integrated circuit in accordance with claim 1 wherein the memory cells are accessed or refreshed in response to a RAS signal, and wherein the timing circuit engages the filter in response to the RAS signal.
Claim 6
Dependent Claim
108 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable low pass filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the low pass filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator; and a timing circuit which engages the low pass filter in response to the presence of a signal, wherein the low pass filter filters the reference voltage for a period of time during which the signal is present.
Claim 7
Dependent Claim
108 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable low pass filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the low pass filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator; and a timing circuit which engages the low pass filter in response to the presence of a signal, wherein the low pass filter filters the reference voltage for a period of time during which the signal is present.
Claim 8
Dependent Claim
17 words
An integrated circuit in accordance with claim 5 wherein the low pass filter includes a resistor-capacitor network.
Claim 9
Dependent Claim
43 words
An integrated circuit in accordance with claim 5 wherein the timing circuit engages the filter in response to presence of a RAS signal, and wherein the low pass filter filters the reference voltage for a period during which a RAS signal is present.
Claim 10
Dependent Claim
23 words
An integrated circuit in accordance with claim 5 wherein the timing circuit engages the filter coincident with the start of a RAS signal.
Claim 11
Dependent Claim
40 words
An integrated circuit in accordance with claim 5 wherein the timing circuit engages the filter coincident with the start of a RAS signal, and for a period of time less than the period during which the RAS signal is present.
Claim 12
Independent Claim
73 words
A method of increasing the speed of operation of a dynamic random access memory having memory cells which are individually accessed in response to a signal, including a reference voltage generator having an output, and including a voltage regulator which accepts the output of the reference voltage generator and supplies voltage to the dynamic random access memory, the method comprising: filtering the output of the reference voltage generator in response to the signal.
Claim 13
Independent Claim
73 words
A method of increasing the speed of operation of a dynamic random access memory having memory cells which are individually accessed in response to a signal, including a reference voltage generator having an output, and including a voltage regulator which accepts the output of the reference voltage generator and supplies voltage to the dynamic random access memory, the method comprising: filtering the output of the reference voltage generator in response to the signal.
Claim 14
Dependent Claim
34 words
A method in accordance with claim 10 wherein the filtering step comprises the step of using a low pass filter to filter the output of the reference voltage generator in response to the signal.
Claim 15
Dependent Claim
14 words
A method in accordance with claim 10 wherein the signal is a RAS signal.
Claim 16
Dependent Claim
58 words
A circuit comprising: a dynamic random access memory having a memory cell, which memory cell is selectively accessed in response to a signal; a voltage regulator which supplies an operating voltage to the dynamic random access memory; and means, including a selectively engageable filter, for maintaining the operating voltage steady during reading and writing to the memory cell.
Claim 17
Dependent Claim
58 words
A circuit comprising: a dynamic random access memory having a memory cell, which memory cell is selectively accessed in response to a signal; a voltage regulator which supplies an operating voltage to the dynamic random access memory; and means, including a selectively engageable filter, for maintaining the operating voltage steady during reading and writing to the memory cell.
Claim 18
Dependent Claim
50 words
A circuit in accordance with claim 13 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage generator, and wherein the filter filters the output of the reference voltage generator in response to the signal.
Claim 19
Dependent Claim
50 words
A circuit in accordance with claim 13 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage regulator, and wherein the filter comprises a low pass filter filtering the output of the reference voltage generator.
Claim 20
Dependent Claim
14 words
A circuit in accordance with claim 13 wherein the signal is a RAS signal.
Claim 21
Dependent Claim
27 words
A circuit in accordance with claim 13 and further comprising an integrated circuit package housing the dynamic random access memory, the voltage regulator, and the maintaining means.
Claim 22
Dependent Claim
54 words
A circuit comprising: a dynamic random access memory having a memory cell which is selectively refreshed in response to a signal; a voltage regulator which supplies an operating voltage to the dynamic random access memory; and means, including a selectively engageable filter, for maintaining the operating voltage steady during refreshing of the memory cell.
Claim 23
Dependent Claim
54 words
A circuit comprising: a dynamic random access memory having a memory cell which is selectively refreshed in response to a signal; a voltage regulator which supplies an operating voltage to the dynamic random access memory; and means, including a selectively engageable filter, for maintaining the operating voltage steady during refreshing of the memory cell.
Claim 24
Dependent Claim
50 words
A circuit in accordance with claim 18 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage generator, and wherein the filter filters the output of the reference voltage generator in response to the signal.
Claim 25
Dependent Claim
50 words
A circuit in accordance with claim 18 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage regulator, and wherein the filter comprises a low pass filter filtering the output of the reference voltage generator.
Claim 26
Dependent Claim
14 words
A circuit in accordance with claim 18 wherein the signal is a RAS signal.
Claim 27
Dependent Claim
27 words
A circuit in accordance with claim 18 and further comprising an integrated circuit package housing the dynamic random access memory, the voltage regulator, and the maintaining means.
Claim 28
Independent Claim
95 words
A system comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a circuit receiving power from the output of the voltage regulator, the system being accessed in response to a first signal; and a timing circuit which engages the filter in response to the first signal, and causes the filter to filter the reference voltage.
Claim 29
Independent Claim
95 words
A system comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a circuit receiving power from the output of the voltage regulator, the system being accessed in response to a first signal; and a timing circuit which engages the filter in response to the first signal, and causes the filter to filter the reference voltage.
Claim 30
Dependent Claim
15 words
A system in accordance with claim 23 wherein the filter is a low pass filter.
Claim 31
Dependent Claim
19 words
A system in accordance with claim 23 wherein the filter comprises a low pass filter including a resistor-capacitor network.
Claim 32
Dependent Claim
118 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; means generating a predictable noise function; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed or refreshed in response to the generating means generating the noise function; and a timing circuit which engages the filter in response to the first signal, and causes the filter to filter the reference voltage.
Claim 33
Dependent Claim
118 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; means generating a predictable noise function; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed or refreshed in response to the generating means generating the noise function; and a timing circuit which engages the filter in response to the first signal, and causes the filter to filter the reference voltage.
Claim 34
Dependent Claim
16 words
An integrated circuit in accordance with claim 26 wherein the filter is a low pass filter.
Claim 35
Dependent Claim
20 words
An integrated circuit in accordance with claim 26 wherein the filter comprises a low pass filter including a resistor-capacitor network.
Claim 36
Dependent Claim
36 words
An integrated circuit in accordance with claim 26 wherein the memory cells are accessed or refreshed in response to a RAS signal, and wherein the timing circuit engages the filter in response to the RAS signal.
Claim 37
Dependent Claim
107 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells; means for refreshing the memory cells; and a timing circuit which engages the filter in response to the refreshing means refreshing the memory cells, and causes the filter to filter the reference voltage.
Claim 38
Dependent Claim
107 words
An integrated circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells; means for refreshing the memory cells; and a timing circuit which engages the filter in response to the refreshing means refreshing the memory cells, and causes the filter to filter the reference voltage.
References Cited (Backward Citations)
US4961167A
Cited
US5163025A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |