US5596505A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Estimation of pin-to-pin timing for compiled blocks
Assignee: Philips Semiconductors Inc
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Filing: 1993-07-23
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Granted: 1997-01-21
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Expires: 2013-07-23
Abstract
Abstract A method for producing an electrical circuit by determining the input-to-output timing of compiled circuit blocks includes steps of determining a signal delay of a component due to physical characteristics of the component. The physical characteristics include at least a capacitance based upon relative placement of the component during compilation of a circuit block. The method further includes steps of determining an input-to-output speed for a circuit block by combining delays due to physical characteristics through alternate paths of the circuit block, and producing a compiled circuit block having a plurality of components by placing the components in the circuit block based on the steps of determining.
Inventors
- 👤 Russell L. Steinweg
- 👤 Michael A. Zampaglione
- 👤 Pei H. Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 01:49
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
81 words
A process for producing an electrical circuit comprising the steps of: determining a signal delay of a component due to physical characteristics of the component, said physical characteristics including at least a capacitance based upon a predetermined relative placement of the component during compilation of a circuit block; determining an input-to-output speed for a circuit block by determining delays due to physical characteristics through alternate paths of the circuit block; and producing a compiled circuit block having said predetermined relative placement.
Claim 2
Dependent Claim
81 words
A process for producing an electrical circuit comprising the steps of: determining a signal delay of a component due to physical characteristics of the component, said physical characteristics including at least a capacitance based upon a predetermined relative placement of the component during compilation of a circuit block; determining an input-to-output speed for a circuit block by determining delays due to physical characteristics through alternate paths of the circuit block; and producing a compiled circuit block having said predetermined relative placement.
Claim 3
Dependent Claim
50 words
A process according to claim 1, wherein said step of determining a signal delay further includes steps of: accessing a stored propagation delay as a physical characteristic of at least one component to be placed in said circuit block; and determining an output load for said at least one component.
Claim 4
Dependent Claim
51 words
A process according to claim 2, wherein said step of determining an output load of said at least one component further includes a step of: combining the input capacitance of additional components that are connected to an output wire of the at least one component and estimating the output wire length.
Claim 5
Dependent Claim
45 words
A process according to claim 3, wherein said step of determining an output load of a component further includes a step of: determining an output load due to wire capacitance based on the estimated output wire length and a value of capacitance per unit length.
Claim 6
Dependent Claim
42 words
A process according to claim 3, wherein said step of combining the input capacitance of additional components connected to the output wire and estimating output wire length further includes a step of: accessing a stored placement sequence when compiling the circuit block.
Claim 7
Dependent Claim
33 words
A process according to claim 5, wherein the step of determining the input-to-output speed further includes a step of: summing pin-to-pin timing delays of components on a signal path through the circuit block.
Claim 8
Dependent Claim
31 words
A process according to claim 3, further including a step of: determining an output load propagation ramp delay of said at least one component as a function of a ramp factor.
Claim 9
Dependent Claim
34 words
A process according to claim 3, further including a step of: determining a critical path having longest pin-to-pin timing delay through a circuit block from a circuit block input to a circuit block output.
Claim 10
Dependent Claim
21 words
A process according to claim 1, wherein said step of determining an input-to-output speed for a circuit block is performed hierarchically.
Claim 11
Dependent Claim
80 words
A process for controlling a block compiler system to produce a compiled circuit block comprising the steps of: determining a signal delay due to physical characteristics of a component, said physical characteristics including at least a capacitance based upon a predetermined relative placement of the component during compilation of a circuit block: and determining input-to-output said for a circuit block by combining delays due to physical characteristics through alternate paths of a compiled circuit block having said predetermined relative placement.
Claim 12
Dependent Claim
80 words
A process for controlling a block compiler system to produce a compiled circuit block comprising the steps of: determining a signal delay due to physical characteristics of a component, said physical characteristics including at least a capacitance based upon a predetermined relative placement of the component during compilation of a circuit block: and determining input-to-output said for a circuit block by combining delays due to physical characteristics through alternate paths of a compiled circuit block having said predetermined relative placement.
Claim 13
Dependent Claim
50 words
A process according to claim 10, wherein said step of determining a signal delay further includes steps of: accessing a stored propagation delay as a physical characteristic of at least one component to be placed in said circuit block; and determining an output load for said at least one component.
Claim 14
Dependent Claim
51 words
A process according to claim 11, wherein said step of determining an output load of said at least one component further includes a step of: combining the input capacitance of additional components that are connected to an output wire of the at least one component and estimating the output wire length.
Claim 15
Dependent Claim
45 words
A process according to claim 12, wherein said step of determining an output load of a component further includes a step of: determining an output load due to wire capacitance based on the estimated output wire length and a value of capacitance per unit length.
Claim 16
Dependent Claim
42 words
A process according to claim 12, wherein said step of combining the input capacitance of additional components connected to the output wire and estimating output wire length further includes a step of: accessing a stored placement sequence when compiling the circuit block.
Claim 17
Dependent Claim
33 words
A process according to claim 14, wherein the step of determining the input-to-output speed further includes a step of: summing pin-to-pin timing delays of components on a signal path through the circuit block.
Claim 18
Dependent Claim
31 words
A process according to claim 12, further including a step of: determining an output load propagation ramp delay of said at least one component as a function of a ramp factor.
Claim 19
Dependent Claim
34 words
A process according to claim 12, further including a step of: determining a critical path having longest pin-to-pin timing delay through a circuit block from a circuit block input to a circuit block output.
Claim 20
Dependent Claim
21 words
A process according to claim 10, wherein said step of determining an input-to-output speed for a circuit block is performed hierarchically.
Claim 21
Dependent Claim
58 words
A process according to claim 18, wherein said steps of hierarchically determining input-to-output speed further include steps of: determining components within each stage which form a critical path through the stage; and determining stages of the circuit block, based on critical paths of each stage, which form the alternate path having a longest delay through the circuit block.
Claim 22
Dependent Claim
25 words
A process according to claim 10, further including a step of: tracking changes in components of the circuit block as primitive models of components changes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |