US5596223A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method of selecting the same
Assignee: NEC Corp
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Filing: 1996-05-21
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Granted: 1997-01-21
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Expires: 2016-05-21
Abstract
Abstract A semiconductor device has a plated heat sink structure. The plated heat sink structure includes an Ni-plating layer.
Inventors
- 👤 Kazunori Asano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:20
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/20; H10W40/22; H10W40/226; H10W40/25; H10W40/255; H10W46/00; H10W46/601
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
138 words
A plurality of semiconductor chips formed on a semiconductor substrate, said plurality of semiconductor chips comprising: at least one group of first semiconductor chips, at least one group of second semiconductor chips, and a plurality of plated heat sink structures formed at respective rear surfaces of said semiconductor chips, each of said plated heat sink structures formed at respective rear surfaces of said at least one group of first semiconductor chips comprising a nickel-plating layer for allowing said at least one group of first semiconductor chips to be selected from among said at least one group of second semiconductor chips without damaging said semiconductor chips and adversely affecting characteristics thereof and, each of said plated heat sink structures formed at respective rear surfaces of said at least one group of second semiconductor chips not comprising any nickel-plating layer.
Claim 2
Dependent Claim
138 words
A plurality of semiconductor chips formed on a semiconductor substrate, said plurality of semiconductor chips comprising: at least one group of first semiconductor chips, at least one group of second semiconductor chips, and a plurality of plated heat sink structures formed at respective rear surfaces of said semiconductor chips, each of said plated heat sink structures formed at respective rear surfaces of said at least one group of first semiconductor chips comprising a nickel-plating layer for allowing said at least one group of first semiconductor chips to be selected from among said at least one group of second semiconductor chips without damaging said semiconductor chips and adversely affecting characteristics thereof and, each of said plated heat sink structures formed at respective rear surfaces of said at least one group of second semiconductor chips not comprising any nickel-plating layer.
Claim 3
Dependent Claim
19 words
The semiconductor chips as claimed in claim 1, wherein an Au-plating layer is further formed on said nickel-plating layer.
Claim 4
Dependent Claim
19 words
The semiconductor chips as claimed in claim 1, wherein said plurality of semiconductor chips are formed on one wafer.
Claim 5
Dependent Claim
51 words
The semiconductor chips as claims in claim 1, wherein each of said at least one group of first semiconductor chips are selected by an electromagnet placed in proximity to said semiconductor substrate such that only each of said at least one group of first semiconductor chips are drawn toward said electromagnet.
Claim 6
Independent Claim
131 words
A method for selecting at least one group of first semiconductor chips from a plurality of semiconductor chips which also include at least one group of second semiconductor chips, comprising the steps of: a) forming plated heat structures at respective rear surfaces of each of said plurality of semiconductor chips, said plated heat structures for said at least one group of first semiconductor chips including a nickel-plating layer, said plated heat structures for said at least one group of second semiconductor chips not including the nickel-plating layer; and b) placing an electromagnet in proximity to said semiconductor chips so as to select said at least one group of semiconductor chips from said plurality of semiconductor chips due to attraction of said at least one group of semiconductor chips towards said electromagnet.
Claim 7
Independent Claim
131 words
A method for selecting at least one group of first semiconductor chips from a plurality of semiconductor chips which also include at least one group of second semiconductor chips, comprising the steps of: a) forming plated heat structures at respective rear surfaces of each of said plurality of semiconductor chips, said plated heat structures for said at least one group of first semiconductor chips including a nickel-plating layer, said plated heat structures for said at least one group of second semiconductor chips not including the nickel-plating layer; and b) placing an electromagnet in proximity to said semiconductor chips so as to select said at least one group of semiconductor chips from said plurality of semiconductor chips due to attraction of said at least one group of semiconductor chips towards said electromagnet.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |