Patent US5594887A successfully refreshed from Google Patents.
US5594887A
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Main memory controller responsive to signals indicative of owned and unowned status
Assignee: Panasonic Holdings Corp
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Filing: 1994-11-01
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Granted: 1997-01-14
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Expires: 2014-11-01
Abstract
Abstract In a system bus connected to at least one CPU having a cache memory used for increasing memory access speed in an engineering workstation or the like, a main memory controller including a status memory for storing owned and unowned statuses in a main memory and a cache memory of data associated with an access operation to a system bus connected to at least one CPU having a cache memory performed by an access means of a CPU or the like, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before the time for outputting a data invalidating signal from the cache memory elapses in the case of the owned status and for reading the data in the cache memory after the data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring accesses to the system bus and for rewriting the status in the status memory according to the result of the monitoring.
Inventors
- 👤 Masataka Osaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:58
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0826; G06F12/0831; G06F2212/00; G06F2212/62; G06F2212/622
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
147 words
A main memory controller comprising: a status memory for storing owned and unowned statuses, in a main memory and a cache memory, of data associated with an access operation to a system bus connected to at least one CPU having a cache memory and performed by an access means of such CPU, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before a time for outputting a data invalidating signal from said cache memory elapses in the case of the owned status, and for reading the data in the cache memory after said data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring accesses to the system bus and for rewriting the status in said status memory according to a result of the monitoring.
Claim 2
Dependent Claim
147 words
A main memory controller comprising: a status memory for storing owned and unowned statuses, in a main memory and a cache memory, of data associated with an access operation to a system bus connected to at least one CPU having a cache memory and performed by an access means of such CPU, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before a time for outputting a data invalidating signal from said cache memory elapses in the case of the owned status, and for reading the data in the cache memory after said data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring accesses to the system bus and for rewriting the status in said status memory according to a result of the monitoring.
Claim 3
Dependent Claim
67 words
The main memory controller according to claim 1, comprising an address decoder for decoding a valid address range of said status memory so that the capacity of said status memory can be maintained constant regardless of an increase in the capacity of the main memory and so that the same operation as that in the unowned status can be performed for invalid addresses in said status memory.
Claim 4
Dependent Claim
156 words
A main memory controller comprising: a status memory for storing owned and unowned statuses, in a main memory and a cache memory, of data associated with an access operation to a system bus connected to at least one CPU having a cache memory and performed by an access means of such CPU, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before a time for outputting a data invalidating signal from said cache memory elapses in the case of the owned status and for reading the data in the cache memory after said data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring an access operation and for rewriting the status, in said status memory, according to the access operation monitored and a status which is before said rewriting in said status memory.
Claim 5
Dependent Claim
156 words
A main memory controller comprising: a status memory for storing owned and unowned statuses, in a main memory and a cache memory, of data associated with an access operation to a system bus connected to at least one CPU having a cache memory and performed by an access means of such CPU, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before a time for outputting a data invalidating signal from said cache memory elapses in the case of the owned status and for reading the data in the cache memory after said data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring an access operation and for rewriting the status, in said status memory, according to the access operation monitored and a status which is before said rewriting in said status memory.
Claim 6
Dependent Claim
67 words
The main memory controller according to claim 3, comprising an address decoder for decoding a valid address range of said status memory so that the capacity of said status memory can be maintained constant regardless of an increase in the capacity of the main memory and so that the same operation as that in the unowned status can be performed for invalid addresses in said status memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |