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US5594864A
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Method and apparatus for unobtrusively monitoring processor states and characterizing bottlenecks in a pipelined processor executing grouped instructions
Assignee: Sun Microsystems Inc
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Filing: 1995-05-30
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Granted: 1997-01-14
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Expires: 2015-05-30
Abstract
Abstract Methods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An instruction queue and an instruction control unit within a pipelined central processor unit (CPU) provide for grouping and issuing multiple instructions per clock cycle for overlapped execution. Additionally, instruction and data caches in operation with integer and floating point function units issue a program counter to the instruction cache, which subsequently supplies instructions to integer and floating point instruction queues. Both integer and floating point unit datapaths comprise fetch, decode, execute, and writeback stages. In the preferred embodiment, ten additional datalines transmitting PIPE signals are routed from the integer and floating point function units to contact pins on an external pin gate array supporting the CPU. The ten PIPE signals provide information on activity of key internal states of the pipelined processor within a single clock cycle. The PIPE signals may be monitored by a logic analyzer, thereby forming an external hardware monitor. By tracing the ten PIPE signals, the number of instructions issued in each stall-free cycle and total number of cycles elapsed may be determined, permitting determination of bottlenecks in customer software on the target CPU, as well as yielding information for optimizing the CPU to execute customer software more efficiently. Based on the accumulated and tabulated performance data, a CPU vendor can reconfigure hardware and/or software to more precisely meet customer workload needs based on determination of customer software operating in the customers actual work environment.
Inventors
- 👤 Richard D. Trauben
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:20
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/25
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
186 words
In a pipelined processor comprising an integer unit pipeline, a floating point unit pipeline, embedded instruction and data caches, and an instruction control unit, a method for unobtrusively monitoring processor states during execution of a proprietary application workload, said method comprising the steps of: issuing and queuing a plurality of sequential instructions to said instruction control unit; issuing and queuing a plurality of branch target instructions to said instruction control unit; tracing a number of completed instructions comprising a sum of said sequential and branch target instructions issued during a stall-free cycle of said pipelined processor including providing a plurality of pins on a pin gate array for transmitting a plurality of PIPE signals; coupling said pins through a coupler to a logic analyzer; and, recording said PIPE signals on said logic analyzer. storing said number of completed instructions, determining the likely cause of a stall ending a stall free cycle based on a plurality of PIPE signals; and, tabulating and logically combining said number of completed instructions to determine said processor states on a cycle by cycle basis during execution of said proprietary application workload.
Claim 2
Dependent Claim
186 words
In a pipelined processor comprising an integer unit pipeline, a floating point unit pipeline, embedded instruction and data caches, and an instruction control unit, a method for unobtrusively monitoring processor states during execution of a proprietary application workload, said method comprising the steps of: issuing and queuing a plurality of sequential instructions to said instruction control unit; issuing and queuing a plurality of branch target instructions to said instruction control unit; tracing a number of completed instructions comprising a sum of said sequential and branch target instructions issued during a stall-free cycle of said pipelined processor including providing a plurality of pins on a pin gate array for transmitting a plurality of PIPE signals; coupling said pins through a coupler to a logic analyzer; and, recording said PIPE signals on said logic analyzer. storing said number of completed instructions, determining the likely cause of a stall ending a stall free cycle based on a plurality of PIPE signals; and, tabulating and logically combining said number of completed instructions to determine said processor states on a cycle by cycle basis during execution of said proprietary application workload.
Claim 3
Dependent Claim
204 words
The method as set forth in claim 1, wherein providing said PIPE signals and tracing said number of completed instructions further comprises: determining a total number of instructions completing execution; if none of said sequential and branch target instructions are executed, determining: whether a pipeline interlock exists, and whether an instruction fetch operation could not be completed in a single cycle; if any of said sequential and branch target instructions are executed, determining if any of said instructions comprise branches, and if so, which branch path is selected; determining if any of said sequential and branch target instructions comprise data memory references, and if so, can such data memory references be supplied to the pipelined processor within the same cycle; determining if any of said sequential and branch target instructions comprise floating point memory references, and if so, can such floating point memory references be supplied to the pipelined processor within a single cycle; determining if any of said sequential and branch target instructions comprise floating point arithmetic instructions, and if so, can such floating point arithmetic instructions be executed without stalling the integer unit pipeline; and, determining if any of said instructions comprise system calls to system software executing on said pipelined processor.
Claim 4
Dependent Claim
55 words
The method as set forth in claim 2, wherein said total number of instructions completing execution are tabulated and logically combined to determine: a current state of said pipelined processor; an instruction mix value; an interrupt rate to said pipelined processor; and, a rate of system calls from said processor to said proprietary application workload.
Claim 5
Dependent Claim
117 words
The method as set forth in claim 3, wherein the step of tracing further comprises the steps of: commencing at a first instruction of said proprietary application workload; executing said sequential and branch target instructions such that said branch target instructions are chosen; and, comparing said current state of said pipelined processor, said instruction mix value, said interrupt rate to said processor, and said rate of system calls, representative of said proprietary application workload following execution of said branch target instructions to said current state of said processor, said instruction mix value, said interrupt rate to said processor, and said rate of system calls, representative of said proprietary application workload without execution of said branch target instructions.
Claim 6
Dependent Claim
233 words
(Amended) The method as set forth in claim 4, wherein the step of providing said PIPE signals further comprises: asserting a first PIPE signal (PIPE0) when an interrupt or a system call is present in an execute stage of said pipelined processor; asserting a second PIPE signal (PIPE1) and a third PIPE signal (PIPE2) representing the number of instructions present in the execute stage of said pipelined processor; asserting a fourth PIPE signal (PIPE3) when a successor instruction of branch instruction comprises a target instruction stream; asserting a fifth PIPE signal (PIPE4) when said pipelined processor is stalled because any floating point arithmetic instruction cannot be completed in a single cycle; asserting a sixth PIPE signal (PIPE5) when said pipelined processor is stalled because said data memory references cannot be completed in a single cycle; asserting a seventh PIPE signal (PIPE6) when no valid instructions are present when any instruction in the execute stage of said pipelined processor was resident in an instruction queue; asserting an eighth PIPE signal (PIPE7) when a valid control transfer instruction is present in the execute stage of said pipelined processor; asserting a ninth PIPE signal (PIPE8) when a valid floating point arithmetic instruction is present in the execute stage of said pipelined processor; and, asserting a tenth PIPE signal (PIPE9) when a valid data memory reference instruction is present in the execute stage of said pipelined processor.
Claim 7
Dependent Claim
38 words
The method according to claim 5, further comprising the steps of: logically combining said fifth and sixth PIPE signals together to form a composite NOR representation thereof; and, latching said composite NOR representation to form a CYCLE0 signal.
Claim 8
Dependent Claim
74 words
The method as set forth in claim 6, wherein the step of forming said CYCLE0 signal further comprises determining an effective data cache miss rate, wherein said data cache miss: occurs in a data translation lookaside buffer; occurs when loading from said embedded data cache; and, occurs when a result store buffer is full and must be emptied before a data memory reference present in the execute stage of said pipelined processor can proceed.
Claim 9
Dependent Claim
79 words
The method as set forth in claim 7, wherein the step of forming said CYCLE0 signal further comprises determining: that an entry in said results store buffer is required by said data memory reference present in the execute stage of said pipelined processor; that a synchronous store instruction is present in the execute stage of said pipelined processor; and, that an atomic access instruction requiring multiple cycles for completing is present in the execute stage of said pipelined processor.
Claim 10
Dependent Claim
101 words
The method as set forth in claim 8, wherein the step of forming said CYCLE0 signal comprises determining an effective frequency of floating point code interlocks, wherein: a floating point queue is full, and there is no capacity to accept a subsequent instruction; a destination register of a floating point Icad instruction is interlocked and must be resolved before such instruction present in the execute stage of said pipelined processor can proceed; a source register of a floating point store instruction is interlocked and must be resolved before such instruction present in the execute stage of said pipelined processor can proceed.
Claim 11
Dependent Claim
91 words
The method as set forth in claim 9, wherein the step of forming said second and third PIPE signals comprises determining an effective instruction cache miss rate, wherein said second and third PIPE signals indicate: an instruction cache miss has occurred in an instruction translation lookaside buffer; an instruction cache miss has occurred when loading from an embedded instruction cache; and, a data dependency between instruction groups exists at different stages of said pipelined processor, wherein said data dependency cannot be resolved by forwarding paths present in said proprietary application workload.
Claim 12
Dependent Claim
55 words
The method as set forth in claim 10, wherein the steps of forming said PIPE and CYCLE0 signals comprise determining an effective frequency and latency between branches, wherein: a percentage of branches taken is computed; an instantaneous and average latency between branches is computed; and, a number of instructions executed between successive branches is tabulated.
Claim 13
Dependent Claim
69 words
The method as set forth in claim 11, wherein the steps of forming said PIPE and CYCLE0 signals comprise determining an effective frequency and latency between a multiplicity of context switches, wherein: a number of entries into an operating system kernel of said pipelined processor are tabulated; an instantaneous and average latency between context switches is computed; and, a number of instructions executed between said context switches is tabulated.
Claim 14
Dependent Claim
202 words
In a pipelined processor comprising art integer unit pipeline, a floating point unit pipeline, embedded instruction and data caches, a monitor system for unobtrusively monitoring processor states during execution of a proprietary application workload, said monitor system comprising: an instruction control unit coupled to said pipelined processor issuing; the instruction control unit queuing a plurality of sequential instructions to said pipelined processor, said instruction control unit further issuing and queuing a plurality of branch target instructions to said pipelined processor; a plurality of pins on a pin gate array coupled to said pipelined processor for transmitting a plurality of PIPE signals; and a logic analyzer coupled to the pins through a coupler for recording the PIPE signals, thereby tracing a number of completed instructions comprising a sum of said sequential and branch target instructions issued during a stall-free cycle of said pipelined processor: said logic analyzer storing said number of completed instructions, and, tabulating and logically combining said number of completed instructions to determine said processor states on a cycle by cycle basis during execution of said proprietary application workload; said logic analyzer further determining the likely cause of a stall ending a stall-free cycle based on a plurality of pipe signals.
Claim 15
Dependent Claim
202 words
In a pipelined processor comprising art integer unit pipeline, a floating point unit pipeline, embedded instruction and data caches, a monitor system for unobtrusively monitoring processor states during execution of a proprietary application workload, said monitor system comprising: an instruction control unit coupled to said pipelined processor issuing; the instruction control unit queuing a plurality of sequential instructions to said pipelined processor, said instruction control unit further issuing and queuing a plurality of branch target instructions to said pipelined processor; a plurality of pins on a pin gate array coupled to said pipelined processor for transmitting a plurality of PIPE signals; and a logic analyzer coupled to the pins through a coupler for recording the PIPE signals, thereby tracing a number of completed instructions comprising a sum of said sequential and branch target instructions issued during a stall-free cycle of said pipelined processor: said logic analyzer storing said number of completed instructions, and, tabulating and logically combining said number of completed instructions to determine said processor states on a cycle by cycle basis during execution of said proprietary application workload; said logic analyzer further determining the likely cause of a stall ending a stall-free cycle based on a plurality of pipe signals.
Claim 16
Dependent Claim
57 words
The monitor system as set forth in claim 13, wherein said total number of instructions completing execution are tabulated and logically combined to determine: a current state of said pipelined processor; an instruction mix value; an interrupt rate to said pipelined processor; and, a rate of system calls from said pipelined processor to said proprietary application workload.
Claim 17
Dependent Claim
121 words
The monitor system as set forth in claim 14, wherein: said pipelined processor commences at the first instruction of said proprietary application workload; said pipelined processor executes said sequential and branch target instructions such that said branch target instructions are chosen; and, said logic analyzer compares said current state of said pipelined processor, said instruction mix value, said interrupt rate to said pipelined processor, and said rate of system calls, representative of said proprietary application workload following execution of said branch target instructions to said current state of said pipelined processor, said instruction mix value, said interrupt rate to said pipelined processor, and said rate of system calls, representative of said proprietary application workload without execution of said branch target instructions.
Claim 18
Dependent Claim
237 words
The monitor system as set forth in claim 15, wherein said monitor system further comprises: a plurality of PIPE signals further comprising: a first PIPE signal (PIPE0) asserted when an interrupt or a system call is present in an execute stage of said pipelined processor; a second PIPE signal (PIPE 1) and a third PIPE signal (PIPE2) representing the number of instructions present in the execute stage of said pipelined processor; a fourth PIPE signal (PIPE3) asserted when a successor instruction of a branch instruction comprises a target instruction stream; a fifth PIPE signal (PIPE4) asserted when said pipelined processor is stalled because any floating point operate instruction cannot be completed in a single cycle; a sixth PIPE signal (PIPE5) asserted when said pipelined processor is stalled because said data memory references cannot be completed in a single cycle; a seventh PIPE signal (PIPE6) asserted when no valid instructions were present when any instruction in the execute stage of said pipelined processor was resident in an instruction cache; an eighth PIPE signal (PIPE7) asserted when a valid control transfer instruction is present in the execute stage of said pipelined processor; a ninth PIPE signal (PIPE8) asserted when a valid floating point arithmetic instruction is present in the execute stage of said pipelined processor; and, a tenth PIPE signal (PIPE9) asserted when a valid data memory reference instruction is present in the execute stage of said pipelined processor.
Claim 19
Dependent Claim
43 words
The monitor system according to claim 16, further comprising; a NOR gate, wherein said fifth and sixth PIPE signals are combined together to form a composite NOR representation thereof; and, a latch for latching said composite NOR representation to form a CYCLE0 signal.
Claim 20
Dependent Claim
70 words
The monitor system as set forth in claim 17, wherein said CYCLE0 signal further comprises an effective data cache miss rate, wherein said data cache miss: occurs in a data translation lookaside buffer; occurs when loading from said embedded data cache; and, occurs when a result store buffer is full and must be emptied before a data memory reference present in the execute stage of said pipelined processor can proceed.
References Cited (Backward Citations)
US4879646A
Cited
US5321828A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |