Apparatus for retiming digital data transmitted at a high speed

Claim 1

An apparatus for retiming digital data transmitted at a high speed, the apparatus comprising: local clock pulse generation means for generating and outputting a local clock pulse; delayed clock pulse parallel generation means for delaying an external clock pulse CP by a period independent of the local clock pulse from said local clock pulse generation means and outputting n delayed clock pulses in parallel, n being a natural number greater than or equal to 4, said delayed clock pulse parallel generation means including a plurality of flip-flops, each of said flip-flops having a minimum allowable clock pulse width; input data transition detection means for receiving an external input data signal D having a unit bit interval with rising and falling portions and for outputting a pulse DT whenever the rising and falling portions are sensed in the external input data signal D, the pulse DT being shorter than the unit bit interval of the external data signal D and longer than the minimum allowable clock pulse width of the flip-flops; sequential logic parallel phase detection means for providing (n-1) clock pulse selection data signals with a logic phase relation between a first transition point of input data signal DT from said input data transition detection means and a second transition point of n delayed clock pulses input from said delayed clock pulse parallel generation means; retiming clock pulse selection means for outputting a retiming clock pulse by getting input of n-1 delayed clock pulses from said delayed clock pulse generation means and by selecting the delayed clock pulse having a nearest falling portion relative to the first transition point of input data signal DT according to the clock pulse selection data signals from said sequential logic parallel phase detection means; time delay compensation means for outputting a compensated signal after compensating the input data signal D by a time delay due to retiming clock pulse selection in said retiming clock pulse selection means; data retiming means for outputting retimed data signals after performing retiming for time compensated signals from said time delay compensation means according to retiming clock pulse input from said retiming clock pulse selection means.

Claim 2

An apparatus for retiming digital data transmitted at a high speed, the apparatus comprising: local clock pulse generation means for generating and outputting a local clock pulse; delayed clock pulse parallel generation means for delaying an external clock pulse CP by a period independent of the local clock pulse from said local clock pulse generation means and outputting n delayed clock pulses in parallel, n being a natural number greater than or equal to 4, said delayed clock pulse parallel generation means including a plurality of flip-flops, each of said flip-flops having a minimum allowable clock pulse width; input data transition detection means for receiving an external input data signal D having a unit bit interval with rising and falling portions and for outputting a pulse DT whenever the rising and falling portions are sensed in the external input data signal D, the pulse DT being shorter than the unit bit interval of the external data signal D and longer than the minimum allowable clock pulse width of the flip-flops; sequential logic parallel phase detection means for providing (n-1) clock pulse selection data signals with a logic phase relation between a first transition point of input data signal DT from said input data transition detection means and a second transition point of n delayed clock pulses input from said delayed clock pulse parallel generation means; retiming clock pulse selection means for outputting a retiming clock pulse by getting input of n-1 delayed clock pulses from said delayed clock pulse generation means and by selecting the delayed clock pulse having a nearest falling portion relative to the first transition point of input data signal DT according to the clock pulse selection data signals from said sequential logic parallel phase detection means; time delay compensation means for outputting a compensated signal after compensating the input data signal D by a time delay due to retiming clock pulse selection in said retiming clock pulse selection means; data retiming means for outputting retimed data signals after performing retiming for time compensated signals from said time delay compensation means according to retiming clock pulse input from said retiming clock pulse selection means.