Fixed duty cycle clock generator

Claim 2

A clock generator responsive to a first clock signal having a frequency f 1 and a second clock signal having a frequency F 2 , wherein f 2 is substantially equal to nf 1 , for generating a fixed duty cycle clock signal having a period equal to n complete cycles of said second clock signal and being at a first level for m complete cycles of said second clock signal and a second level for n-m complete cycles of said second clock signal, said clock generator comprising: an output; counting means responsive to said second clock signal for repeatedly counting half-cycles of said second clock signal during repeated counting periods for providing at said output said first level during said m complete cycles of said second clock signal and said second level during said n-m complete cycles of said second clock signal said counting means including means for establishing a timing condition responsive to said first clock signal; and inhibit means coupled to said counting means for precluding said counting means from beginning a new counting period until said counting means has counted n complete cycles of said second clock signal and for enabling said counting means to begin said new counting period responsive to said counting means counting said n complete cycles of said second clock signal and the establishment of said timing condition.

Claim 3

A clock generator as defined in claim 1 wherein said counting means includes an input and wherein said inhibit means are coupled between said output and said counting means input.

Claim 4

A clock generator as defined in claim 2 wherein said inhibit means are responsive to said second clock signal for enabling said counting means after the last half-cycle of each said counting period.

Claim 5

A clock generator as defined in claim 3 wherein said inhibit means includes latch means having a clock input coupled to said second clock signal.

Claim 6

A clock generator responsive to a first clock signal having a frequency f 1 and a second clock signal having a frequency f 2 , wherein f 2 is substantially equal to nf 1 , for generating a fixed duty cycle clock signal having a period equal to n complete cycles of said second clock signal and being at a first level for m complete cycles of said second clock signal and a second level for n-m complete cycles of said second clock signal, said clock generator comprising: an output; counting means responsive to said second clock signal for repeatedly counting half-cycles of said second clock signal during repeated counting periods for providing at said output said first level during said m complete cycles of said second clock signal and said second level during said n-m complete cycles of said second clock signal said counting means including means for establishing a timing condition responsive to said first clock signal; inhibit means coupled to said counting means for precluding said counting means from beginning a new counting period until said counting means has counted n complete cycles of said second clock signal and for enabling said counting means to begin said new counting period responsive to said counting means counting said n complete cycles of said second clock signal and the establishment of said timing condition; said counting means including an input and said inhibit means being coupled between said output and said counting means input; said inhibit means being responsive to said second clock signal for enabling said counting means after the last half-cycle of each said counting period; said inhibit means including latch means having a clock input coupled to said second clock signal; and said latch means clock input comprising a first clock input coupled to said second clock signal and a second clock input coupled to the complement of said second clock signal.

Claim 7

A clock generator responsive to a first clock signal having a frequency f 1 and a second clock signal having a frequency f 2 , wherein f 2 is substantially equal to nf 1 , for generating a fixed duty cycle clock signal having a period equal to n complete cycles of said second clock signal and being at a first level for m complete cycles of said second clock signal and a second level for n-m complete cycles of said second clock signal, said clock generator comprising: an output; counting means responsive to said second clock signal for repeatedly counting half-cycles of said second clock signal during repeated counting periods for providing at said output said first level during said m complete cycles of said second clock signal and said second level during said n-m complete cycles of said second clock signal said counting means including means for establishing a timing condition responsive to said first clock signal; inhibit means coupled to said counting means for precluding said counting means from beginning a new counting period until said counting means has counted n complete cycles of said second clock signal and for enabling said counting means to begin said new counting period responsive to said counting means counting said n complete cycles of said second clock signal and the establishment of said timing condition; said counting means including an input and said inhibit means being coupled between said output and said counting means input; said inhibit means being responsive to said second clock signal for enabling said counting means after the last half-cycle of each said counting period; said inhibit means including latch means having a clock input coupled to said second clock signal; and said latch means clock input comprising a first clock input coupled to said second clock signal and a second clock input coupled to the complement of said second clock signal.

Claim 8

A clock generator as defined in claim 5 wherein said inhibit means further includes gate means coupled between said latch means output and said counting means input.

Claim 9

A clock generator as defined in claim 6 wherein said gate means includes a first input coupled to said latch means output, a second input responsive to said timing condition, and an output coupled to said counting means input.

Claim 10

A clock generator as defined in claim 7 wherein said means for establishing a timing condition includes a flip-flop and wherein said gate means second input is coupled to said flip-flop.

Claim 11

A clock generator as defined in claim 8 wherein said flip-flop comprises a pair of latches.

Claim 12

A clock generator as defined in claim 7 wherein said gate means comprises a NOR gate.

Claim 13

A clock generator as defined in claim 1 wherein n is equal to four and wherein m is equal to one.

Claim 14

A clock generator as defined in claim 1 wherein said first level is a logical one and said second level is a logical zero.

Claim 15

A clock generator responsive to a first clock signal having a frequency f 1 and a second clock signal having a frequency f 2 , wherein f 2 is substantially equal to 4f 1 , for generating a fixed duty cycle clock signal having a period equal to four complete cycles of said second clock signal, a first level for one complete cycle of said second clock signal, and a second level for three complete cycles of said second clock signal, said clock generator comprising: an output; counting means responsive to said second clock signal for repeatedly counting, during repeated counting periods, eight half-cycles of said second clock signal for providing at said output said first level during two half-cycles of said second clock signal and said second level during six half-cycles of said second clock signal said counting means including means for establishing a timing condition responsive to said first clock signal; and inhibit means coupled to said counting means for precluding said counting means from beginning a new counting period until said counting means has counted eight complete half-cycles of said second clock signal and for enabling said counting means to begin said new counting period responsive to said counting means counting said eight complete half-cycles of said second clock signal and the establishment of said timing condition.

Claim 16

A clock generator responsive to a first clock signal having a frequency f 1 and a second clock signal having a frequency f 2 , wherein f 2 is substantially equal to 4f 1 , for generating a fixed duty cycle clock signal having a period equal to four complete cycles of said second clock signal, a first level for one complete cycle of said second clock signal, and a second level for three complete cycles of said second clock signal, said clock generator comprising: an output; counting means responsive to said second clock signal for repeatedly counting, during repeated counting periods, eight half-cycles of said second clock signal for providing at said output said first level during two half-cycles of said second clock signal and said second level during six half-cycles of said second clock signal said counting means including means for establishing a timing condition responsive to said first clock signal; and inhibit means coupled to said counting means for precluding said counting means from beginning a new counting period until said counting means has counted eight complete half-cycles of said second clock signal and for enabling said counting means to begin said new counting period responsive to said counting means counting said eight complete half-cycles of said second clock signal and the establishment of said timing condition.

Claim 17

A clock generator as defined in claim 13 wherein said inhibit means are responsive to said second clock signal for precluding said counting means from beginning a new counting period until said counting means has counted a complete eighth half-cycle of said second clock signal.

Claim 18

A clock generator as defined in claim 14 wherein said counting means are arranged to provide said second level during the first five half-cycles of said second clock signal, said first level during the sixth and seventh half-cycles of said second clock signal, and said second level during the eighth half-cycle of said second clock signal.

Claim 19

A clock generator as defined in claim 15 wherein said inhibit means are responsive to said second level during said eighth half-cycle of said second clock signal for precluding said counting means from beginning a new counting period.

Claim 20

A clock generator responsive to a first clock signal having a frequency f 1 and a second clock signal having a frequency f 2 , wherein f 2 is substantially equal to 4f 1 , for generating a fixed duty cycle clock signal having a period equal to four complete cycles of said second clock signal, a first level for one complete cycle of said second clock signal, and a second level for three complete cycles of said second clock signal, said clock generator comprising: an output; counting means responsive to said second clock signal for repeatedly counting, during repeated counting periods, eight half-cycles of said second clock signal for providing at said output said first level during two half-cycles of said second clock signal and said second level during six half-cycles of said second clock signal said counting means including means for establishing a timing condition responsive to said first clock signal; inhibit means coupled to said counting means for precluding said counting means from beginning a new counting period until said counting means has counted eight complete half-cycles of said second clock signal and for enabling said counting means to begin said new counting period responsive to said counting means counting said eight complete half-cycles of said second clock signal and the establishment of said timing condition; said inhibit means being responsive to said second clock signal for precluding said counting means from beginning a new counting period until said counting means has counted a complete eighth half-cycle of said second clock signal; said counting means being arranged to provide said second level during the first five half-cycles of said second clock signal, said first level during the sixth and seventh half-cycles of said second clock signal, and said second level during the eighth half-cycle of said second clock signal; said inhibit means being responsive to said second level during said eighth half-cycle of said second clock signal for precluding said counting means from beginning a new counting period; and said counting means comprising a plurality of serially coupled latches, a first one of said latches including the input of said counting means, and at least one of said latches including said circuit output, and said inhibit means comprising a further latch having an input coupled to said output and an output coupled to said counting means input.

Claim 21

A clock generator responsive to a first clock signal having a frequency f 1 and a second clock signal having a frequency f 2 , wherein f 2 is substantially equal to 4f 1 , for generating a fixed duty cycle clock signal having a period equal to four complete cycles of said second clock signal, a first level for one complete cycle of said second clock signal, and a second level for three complete cycles of said second clock signal, said clock generator comprising: an output; counting means responsive to said second clock signal for repeatedly counting, during repeated counting periods, eight half-cycles of said second clock signal for providing at said output said first level during two half-cycles of said second clock signal and said second level during six half-cycles of said second clock signal said counting means including means for establishing a timing condition responsive to said first clock signal; inhibit means coupled to said counting means for precluding said counting means from beginning a new counting period until said counting means has counted eight complete half-cycles of said second clock signal and for enabling said counting means to begin said new counting period responsive to said counting means counting said eight complete half-cycles of said second clock signal and the establishment of said timing condition; said inhibit means being responsive to said second clock signal for precluding said counting means from beginning a new counting period until said counting means has counted a complete eighth half-cycle of said second clock signal; said counting means being arranged to provide said second level during the first five half-cycles of said second clock signal, said first level during the sixth and seventh half-cycles of said second clock signal, and said second level during the eighth half-cycle of said second clock signal; said inhibit means being responsive to said second level during said eighth half-cycle of said second clock signal for precluding said counting means from beginning a new counting period; and said counting means comprising a plurality of serially coupled latches, a first one of said latches including the input of said counting means, and at least one of said latches including said circuit output, and said inhibit means comprising a further latch having an input coupled to said output and an output coupled to said counting means input.

Claim 22

A clock generator as defined in claim 17 wherein said inhibit means further include gate means coupled said further latch output to said counting means input.

Claim 23

A clock generator as defined in claim 18 wherein said gate means has a first input coupled to said further latch output and a second input coupled to said means for establishing a timing condition.

Claim 24

A clock generator as defined in claim 19 wherein said means for establishing a timing condition includes a flip-flop, and wherein said gate means second input is coupled to said flip-flop.

Claim 25

A clock generator as defined in claim 20 wherein said plurality of latches comprises five latches.

Claim 26

A clock generator as defined in claim 21 wherein said gate means comprises a NOR gate.

Claim 27

A clock generator as defined in claim 13 wherein said first level is a logical one and said second level is a logical zero.