US5594361A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic gate with controllable hysteresis and high frequency voltage controlled oscillator
Assignee: Renesas Electronics America Inc
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Filing: 1995-06-06
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Granted: 1997-01-14
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Expires: 2015-06-06
Abstract
Abstract A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.5 nanosecond existing between the squarewave signals on the output terminals.
Inventors
- 👤 David L. Campbell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:17
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/353; H03K3/356; H03K3/3565; H03L7/08; H03L7/099
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
438 words
A circuit having an input lead and an output lead, said circuit comprising: a first logic section having an input lead connected to said input lead of said circuit, an output lead, a first supply voltage lead, and a second supply voltage lead, said first logic section comprising a first complementary symmetry inverter; a second logic section having an input lead, an output lead connected to said output lead of said circuit, a first supply voltage lead, and a second supply voltage lead, said second logic section comprising a second complementary symmetry inverter, said input lead of said second logic section coupled to said output lead of said first logic section; and a hysteresis control section having a first lead, a second lead, a third lead and a supply voltage lead, said first lead coupled to said output lead of said first logic section, said second lead coupled to said output lead of said second logic section, said third lead coupled to said input lead of said first logic section, said hysteresis control section comprising: a first P-channel field effect transistor having a gate, a source and a drain, said gate of said first P-channel field effect transistor being coupled to said input lead of said first logic section, said drain of said first P-channel field effect transistor being coupled to said input lead of said second logic section; a second P-channel field effect transistor having a gate, a source and a drain, said gate of said second P-channel field effect transistor being coupled to said output lead of said second logic section, said drain of said second P-channel field effect transistor being coupled to said source of said first P-channel field effect transistor, said source of said second P-channel field effect transistor being coupled to said first supply voltage lead of said second logic section; a first N-channel field effect transistor having a gate, a source and a drain, said gate of said first N-channel field effect transistor being coupled to said input lead of said first logic section, said drain of said first N-channel field effect transistor being coupled to said input lead of said second logic section; and a second N-channel field effect transistor having a gate, a source and a drain, said gate of said second N-channel field effect transistor being coupled to said output lead of said second logic section, said drain of said second N-channel field effect transistor being coupled to said source of said first N-channel field effect transistor, said source of said second N-channel field effect transistor being coupled to said second supply voltage lead of said second logic section.
Claim 2
Dependent Claim
438 words
A circuit having an input lead and an output lead, said circuit comprising: a first logic section having an input lead connected to said input lead of said circuit, an output lead, a first supply voltage lead, and a second supply voltage lead, said first logic section comprising a first complementary symmetry inverter; a second logic section having an input lead, an output lead connected to said output lead of said circuit, a first supply voltage lead, and a second supply voltage lead, said second logic section comprising a second complementary symmetry inverter, said input lead of said second logic section coupled to said output lead of said first logic section; and a hysteresis control section having a first lead, a second lead, a third lead and a supply voltage lead, said first lead coupled to said output lead of said first logic section, said second lead coupled to said output lead of said second logic section, said third lead coupled to said input lead of said first logic section, said hysteresis control section comprising: a first P-channel field effect transistor having a gate, a source and a drain, said gate of said first P-channel field effect transistor being coupled to said input lead of said first logic section, said drain of said first P-channel field effect transistor being coupled to said input lead of said second logic section; a second P-channel field effect transistor having a gate, a source and a drain, said gate of said second P-channel field effect transistor being coupled to said output lead of said second logic section, said drain of said second P-channel field effect transistor being coupled to said source of said first P-channel field effect transistor, said source of said second P-channel field effect transistor being coupled to said first supply voltage lead of said second logic section; a first N-channel field effect transistor having a gate, a source and a drain, said gate of said first N-channel field effect transistor being coupled to said input lead of said first logic section, said drain of said first N-channel field effect transistor being coupled to said input lead of said second logic section; and a second N-channel field effect transistor having a gate, a source and a drain, said gate of said second N-channel field effect transistor being coupled to said output lead of said second logic section, said drain of said second N-channel field effect transistor being coupled to said source of said first N-channel field effect transistor, said source of said second N-channel field effect transistor being coupled to said second supply voltage lead of said second logic section.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein said circuit is a non-inverting logic gate.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |