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Patent US5592659A successfully refreshed from Google Patents.
US5592659A
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Timing signal generator
Assignee: Yokogawa Electric Corp
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Filing: 1995-10-30
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Granted: 1997-01-07
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Expires: 2015-10-30
Abstract
Abstract A timing signal generator wherein a rate signal generator applies clock signals whose phases are continuous and rate signals to a timing generator wherein delay times and fractional data available within the timing generator are used to thereby generate timing pulses without the need for rate fractional data to be applied from outside the timing generator so that the system is considerably simplified.
Inventors
- 👤 Akira Toyama
- 👤 Tatsuyuki Agata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:52
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H03K5/14; H03K2005/00013; H03K2005/00019; H03K2005/00058
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
252 words
A timing signal generator comprising: a rate generator means for generating a reference clock and rate signal; and a timing generator means for receiving said reference clock and said rate signal from said rate signal generator means, and for generating an edge signal having a user defined delay period; wherein said rate generator means comprises: clock generating means for generating said reference clock having a fixed period; first memory means for storing periodic data; first adder means for adding said periodic data obtained from said first memory means to fractional data of rate timing data from a previous cycle; and rate signal generating means for receiving said reference clock and said rate timing data, and for generating a rate signal having a predetermined resolution which corresponds to said periodic data; and wherein said timing generator means comprises: second memory means for storing data of said delay period; third memory means for storing fractional data of data corresponding to said periodic data stored in said first memory means; second adder means for adding said fractional data obtained from said third memory means to fractional data of a previous cycle; third adder means for adding said data of said delay period obtained from said second memory means to data from said second adder means to produce edge timing data; and timing pulse generating means for receiving said reference clock and said rate signal, and for generating a delay pulse which is initialized by said rate signal and which corresponds to said edge timing data.
Claim 2
Dependent Claim
252 words
A timing signal generator comprising: a rate generator means for generating a reference clock and rate signal; and a timing generator means for receiving said reference clock and said rate signal from said rate signal generator means, and for generating an edge signal having a user defined delay period; wherein said rate generator means comprises: clock generating means for generating said reference clock having a fixed period; first memory means for storing periodic data; first adder means for adding said periodic data obtained from said first memory means to fractional data of rate timing data from a previous cycle; and rate signal generating means for receiving said reference clock and said rate timing data, and for generating a rate signal having a predetermined resolution which corresponds to said periodic data; and wherein said timing generator means comprises: second memory means for storing data of said delay period; third memory means for storing fractional data of data corresponding to said periodic data stored in said first memory means; second adder means for adding said fractional data obtained from said third memory means to fractional data of a previous cycle; third adder means for adding said data of said delay period obtained from said second memory means to data from said second adder means to produce edge timing data; and timing pulse generating means for receiving said reference clock and said rate signal, and for generating a delay pulse which is initialized by said rate signal and which corresponds to said edge timing data.
Claim 3
Dependent Claim
43 words
The generator of claim 1, wherein said rate signal generating means comprises a counter means for counting said reference clock and digital comparator means for comparing counted data obtained from said counter means with said rate timing data from said first adder means.
Claim 4
Dependent Claim
72 words
The generator of claim 1, wherein said timing pulse generating means comprises counter means for counting said reference clock and being reset by said rate signal; digital comparator means for comparing counted dats from said counter means with edge timing data from said third adder means; and delay means for delaying a pulse generated by said digital comparator means in response to a least significant fractional data of said edge timing data.
Claim 5
Dependent Claim
51 words
The generator of claim 1, wherein said rate signal generating means comprises counter means for receiving said rate timing data from said adder means as a preset value and for counting downward said reference clock; and zero detecting means for detecting when the value of said counter means has reached zero.
Claim 6
Dependent Claim
63 words
The generator of claim 1, wherein said timing pulse generating means comprises counter means for receiving as a preset value edge timing data from said third adder means and being reset by said rate signal from said rate signal generating means, and for counting downward said reference clock, and zero detecting means for detecting when the value of said counter means reaches zero.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |