Processor architecture supporting multiple speculative branches and trap handling

Claim 1

A data processing system that performs operations responsive to a program including a plurality of instructions, the instructions including at least a first and second test instruction and at least a first and second branch instruction that determine an intended sequence of execution of the instructions within the program responsive to results of the first and second test instructions respectively, the system comprising: an operation unit that executes the instructions by performing operations responsive to the instructions; a branch prediction unit that speculates a first intended sequence of execution of the instructions responsive to the first branch instruction and speculates a second intended sequence of execution of the instructions responsive to the second branch instruction, the first and second intended sequences affecting sequence of execution of instructions by the operation unit; an instruction shelving unit; a fetching unit that continuously fetches instructions from an instruction memory responsive to said first and second intended sequences and that stores operations to be performed responsive to said instruction in said instruction shelving unit; an evaluation unit that determines, responsive to execution of the first test instruction by the operation unit, whether the branch prediction unit has speculated the first intended sequence correctly, wherein the branch prediction unit speculates the second intended sequence prior to execution of the first test instruction; a repair unit that, upon a determination by the evaluation unit that the branch unit has speculated either the first intended sequence or the second intended sequence incorrectly, nullifies the effects of instructions of the incorrectly speculated intended sequence; a temporary result storage unit that stores results of the operations performed responsive to the instructions, the results including the presence or absence of a trapping condition for a potentially-trapping operation, and wherein the repair unit nullifies an instruction by reversing any update of results to the result storage unit affected by the nullified instruction and preventing any further update of results to the result storage unit by any future performance of operations responsive to the nullified instruction; a register unit; and a retirement and flushing unit that retires instructions if the operations performed responsive to the instructions are not potentially trapping or their results are absent a trapping condition by updating the register unit with the results, and that flushes the performed operation and all following operations from the instruction shelving unit if the performed operation's result indicates the presence of a trapping condition by preventing the performance of these operations from updating the register unit, and that forces the fetching unit to re-fetch the instruction immediately following the instruction corresponding to the operation whose result indicates the presence of a trapping condition, the retiring and flushing unit disposing each instruction in the order of appearance in the sequence.