Regulated complementary charge pump circuit

Claim 2

A charge pump circuit comprising: a first switch pass gate coupled to a high node and a charge pump output for coupling said high node to said charge pump output; a second switch pass gate coupled to a low node and said charge pump output for coupling said low node to said charge pump output; a high node regulator coupled to a source voltage for said charge pump circuit and said first switch pass gate and coupled to receive said charge pump output, for generating a high node voltage at said high node, said high node voltage being regulated above a predetermined margin of said charge pump output; and a low node regulator coupled to ground and said second switch pass gate and coupled to receive said charge pump output, for generating a low node voltage at said low node, said low node voltage being below a predetermined margin of said charge pump output.

Claim 3

The circuit as set forth in claim 1, wherein: said high node regulator comprises two p-channel transistors, a first p-channel transistor being coupled between said source voltage and said high node and a second p-channel transistor being coupled between said high node and ground and being controlled by said charge pump output so as to maintain said high node voltage one p-channel threshold voltage above said charge pump output; and said low node regulator comprises two n-channel transistors, a first n-channel transistor being coupled between said ground and said low node and a second n-channel transistor being coupled between said low node and said source voltage and being controlled by said charge pump output so as to maintain said low node voltage one n-channel threshold voltage below said charge pump output.

Claim 4

The circuit as set forth in claim 1, wherein said first switch pass gate and said second switch pass gate comprise complementary switches.

Claim 5

The circuit as set forth in claim 3, wherein said complementary switches comprise: a first complementary metal oxide semiconductor (CMOS) inverter coupled to said up control signal and for inverting said up control signal; a second complementary metal oxide semiconductor (CMOS) inverter coupled to said down control signal and for inverting said down control signal; a first p-channel transistor coupled to said high node and said charge pump output and being controlled by said first CMOS inverter; and a first n-channel transistor coupled to said high node and said charge pump output and being controlled by said down control signal; a second p-channel transistor coupled to said low node and said charge pump output and being controlled by said second CMOS inverter; and a second n-channel transistor coupled to said low node and said charge pump output and being controlled by said down control signal.

Claim 6

The circuit as set forth in claim 1, further comprising gain resistance coupled to said charge pump output for controlling the gain of said charge pump output.

Claim 7

A phase lock loop comprising: a phase/frequency detector coupled to receive two frequency signals for generating an up control signal and a down control signal representing a phase difference between said two frequency signals; a charge pump circuit coupled to receive said up control signal and said down control signal and for generating charge at a charge pump output in accordance with said up control signal and said down control signal, said charge pump circuit comprising: a first switch pass gate coupled to a high node and said charge pump output for coupling said high node to said charge pump output; a second switch pass gate coupled to a low node and said charge pump output for coupling said low node to said charge pump output; a high node regulator coupled to a source voltage for said charge pump circuit and said first switch pass gate and coupled to receive said charge pump output, for generating a high node voltage at said high node, said high node voltage being regulated a predetermined margin above said charge pump output; a low node regulator coupled to ground and said second switch pass gate and coupled to receive said charge pump output, for generating a low node voltage at said low node, said low node voltage being a predetermined margin below said charge pump output; a loop capacitor coupled to said charge pump output for storing said charge; and a voltage controlled oscillator coupled to said loop capacitor for generating an output frequency locked to a first of said two frequency signals.

Claim 8

A phase lock loop comprising: a phase/frequency detector coupled to receive two frequency signals for generating an up control signal and a down control signal representing a phase difference between said two frequency signals; a charge pump circuit coupled to receive said up control signal and said down control signal and for generating charge at a charge pump output in accordance with said up control signal and said down control signal, said charge pump circuit comprising: a first switch pass gate coupled to a high node and said charge pump output for coupling said high node to said charge pump output; a second switch pass gate coupled to a low node and said charge pump output for coupling said low node to said charge pump output; a high node regulator coupled to a source voltage for said charge pump circuit and said first switch pass gate and coupled to receive said charge pump output, for generating a high node voltage at said high node, said high node voltage being regulated a predetermined margin above said charge pump output; a low node regulator coupled to ground and said second switch pass gate and coupled to receive said charge pump output, for generating a low node voltage at said low node, said low node voltage being a predetermined margin below said charge pump output; a loop capacitor coupled to said charge pump output for storing said charge; and a voltage controlled oscillator coupled to said loop capacitor for generating an output frequency locked to a first of said two frequency signals.

Claim 9

The phase lock loop as set forth in claim 6, wherein said loop capacitor comprises an on-chip capacitor.

Claim 10

The phase lock loop as set forth in claim 6, wherein: said high node regulator comprises two p-channel transistors, a first p-channel transistor being coupled between said source voltage and said high node and a second p-channel transistor being coupled between said high node and ground and being controlled by said charge pump output so as to maintain said high node voltage one p-channel threshold voltage above said charge pump output; and said low node regulator comprises two n-channel transistors, a first n-channel transistor being coupled between said ground and said low node and a second n-channel transistor being coupled between said low node and said source voltage and being controlled by said charge pump output so as to maintain said low node voltage one n-channel threshold voltage below said charge pump output.

Claim 11

The phase lock loop as set forth in claim 6, wherein said first switch pass gate and said second switch pass gate comprise complementary switches.

Claim 12

The phase lock loop as set forth in claim 9, wherein said complementary switches comprise: a first complementary metal oxide semiconductor (CMOS) inverter coupled to said up control signal and for inverting said up control signal; a second complementary metal oxide semiconductor (CMOS) inverter coupled to said down control signal and for inverting said down control signal; a first p-channel transistor coupled to said high node and said charge pump output and being controlled by said first CMOS inverter; and a first n-channel transistor coupled to said high node and said charge pump output and being controlled by said down control signal; a second p-channel transistor coupled to said low node and said charge pump output and being controlled by said second CMOS inverter; and a second n-channel transistor coupled to said low node and said charge pump output and being controlled by said down control signal.

Claim 13

The circuit as set forth in claim 6, further comprising gain resistance coupled to said charge pump output for controlling the gain of said charge pump output.

Claim 16

The method as set forth in claim 12, wherein: the step of generating a high node voltage comprises the steps of: coupling a first p-channel transistor between said source voltage and said high node; coupling a second p-channel transistor between said high node and ground; coupling said charge pump output to said second p-channel transistor so as to maintain said high node voltage one p-channel threshold voltage above said charge pump output; and the step of generating a low node voltage comprises the steps of: coupling a first n-channel transistor between said ground and said low node; coupling a second n-channel transistor between said low node and said source voltage; and coupling said charge pump output to said second n-channel transistor so as to maintain said low node voltage one n-channel threshold voltage below said charge pump output.

Claim 17

The method as set forth in claim 12, wherein: the step of coupling said high node to said charge pump output comprises the step of coupling said high node to said charge pump output with a complementary switch; and the step of coupling said low node to said charge pump output comprises the step coupling said low node to said charge pump output with a complementary switch.

Claim 18

The method as set forth in claim 14, wherein: the step of coupling said high node to said charge pump output with a complementary switch comprises the steps of: coupling a first complementary metal oxide semiconductor (CMOS) inverter to said up control signal; coupling a first p-channel transistor between said high node and said charge pump output and to said first CMOS inverter; coupling a first n-channel transistor between said high node and said charge pump output and to said down control signal; the step of coupling said low node to said charge pump output comprises the steps of: coupling a second complementary metal oxide semiconductor (CMOS) inverter to said down control signal; coupling a second p-channel transistor between said low node and said charge pump output and to said second CMOS inverter; and coupling a second n-channel transistor between said low node and said charge pump output and to said down control signal.