Digital convergence apparatus

Claim 2

A digital convergence apparatus, comprising: a first memory storing convergence correction data for plural correction executing points aligned in a horizontal or vertical direction on a screen; a first static convergence compensation data memory storing a first static convergence compensation data for correcting the entire screen in the same direction; a second static convergence compensation data memory for storing a second static convergence compensation data which is different from the first static convergence compensation data by an amount based on a distance between scanning lines; selecting means for producing a selected output by selecting an output from the first or the second static convergence compensation data memory in response to an odd field period or an even field period; adding means for generating an added output by adding output from the first memory and the selected output; vertical interpolation means for generating interpolated output by interpolating the added output in the vertical direction; and a convergence correction coil correcting convergence based on the interpolated output.

Claim 3

A digital convergence apparatus as claimed in claim 1, wherein the convergence correction data stored in the first memory, the first static convergence compensation data and the second static convergence compensation data include data assigned for correcting the convergence in the horizontal and vertical directions of the screen, and the convergence correction coil includes coils that are used to perform convergence corrections in the horizontal and vertical directions of the screen, respectively.

Claim 4

A digital convergence apparatus of claim 1, wherein the convergence correction data stored in the first memory comprises convergence compensation data assigned to the correction executing points on a prescribed horizontal scanning line and differential data between the convergence compensation data of the correction executing points which are mutually adjacent in the vertical direction.

Claim 5

A digital convergence apparatus comprising: a horizontal convergence compensation data memory storing horizontal convergence compensation data for a plurality of correction executing points, the horizontal convergence compensation data for correcting convergence in the horizontal direction on a screen; a vertical convergence compensation data memory storing vertical convergence compensation data for the plurality of correction executing points, the vertical convergence compensation data for correcting convergence in the vertical direction on the screen; a horizontal static convergence data memory storing a horizontal static convergence compensation data for correcting convergence in the horizontal direction on the entire screen; a first static convergence compensation data memory storing a first static convergence compensation data for correcting convergence on the entire screen in the vertical direction; a second static convergence compensation data memory storing a second static convergence compensation data that is different from the first static convergence compensation data by an amount based on a distance between scanning lines; address control means for controlling readout from the horizontal and vertical convergence compensation data memories; selecting means for producing a selected output by selecting an output from the first or the second static convergence compensation data memory in response to an odd field period or an even field period; horizontal adding means for generating a horizontal added output by adding the convergence compensation data stored in the horizontal convergence compensation data memory with the horizontal static convergence compensation data; vertical adding means for generating a vertical added output by adding the vertical convergence compensation data stored in the vertical convergence compensation data memory with output from the selecting means; horizontal interpolation means for generating horizontal interpolated output by calculating a convergence compensation data at a prescribed position between horizontally adjacent correction executing points based on the horizontal added output; vertical interpolation means for generating vertical interpolated output by calculating a convergence compensation data at a prescribed position between vertically adjacent correction executing points based on the vertical added output; a horizontal convergence correction coil to which the horizontal interpolated output is supplied; and a vertical convergence correction coil to which the vertical interpolated output is supplied.

Claim 6

A digital convergence apparatus comprising: a horizontal convergence compensation data memory storing horizontal convergence compensation data for a plurality of correction executing points, the horizontal convergence compensation data for correcting convergence in the horizontal direction on a screen; a vertical convergence compensation data memory storing vertical convergence compensation data for the plurality of correction executing points, the vertical convergence compensation data for correcting convergence in the vertical direction on the screen; a horizontal static convergence data memory storing a horizontal static convergence compensation data for correcting convergence in the horizontal direction on the entire screen; a first static convergence compensation data memory storing a first static convergence compensation data for correcting convergence on the entire screen in the vertical direction; a second static convergence compensation data memory storing a second static convergence compensation data that is different from the first static convergence compensation data by an amount based on a distance between scanning lines; address control means for controlling readout from the horizontal and vertical convergence compensation data memories; selecting means for producing a selected output by selecting an output from the first or the second static convergence compensation data memory in response to an odd field period or an even field period; horizontal adding means for generating a horizontal added output by adding the convergence compensation data stored in the horizontal convergence compensation data memory with the horizontal static convergence compensation data; vertical adding means for generating a vertical added output by adding the vertical convergence compensation data stored in the vertical convergence compensation data memory with output from the selecting means; horizontal interpolation means for generating horizontal interpolated output by calculating a convergence compensation data at a prescribed position between horizontally adjacent correction executing points based on the horizontal added output; vertical interpolation means for generating vertical interpolated output by calculating a convergence compensation data at a prescribed position between vertically adjacent correction executing points based on the vertical added output; a horizontal convergence correction coil to which the horizontal interpolated output is supplied; and a vertical convergence correction coil to which the vertical interpolated output is supplied.

Claim 7

A digital convergence apparatus, comprising: a first memory storing convergence correction data for a plurality of correction executing points aligned in horizontal or vertical direction on a screen; a static convergence data memory storing a static convergence correction data for correcting the entire screen in the same direction; an offset data memory storing a first offset data for an odd field and a second offset data for an even field, the first and second offset data being used to offset the static convergence correction data, second offset data being based on a distance between scanning lines; selecting means for producing selected output by selectively reading the first or the second offset data stored in the offset data memory according to the odd field period or the even field period; adding means for generating added output by correcting the static convergence correction data stored in the static convergence data memory based on the selected output and adding the corrected static convergence correction data to the convergence correction data stored in the first memory; vertical interpolating means for generating vertical interpolated output by interpolating the added output in the vertical direction; and a convergence correction coil correcting convergence based on the vertical interpolated output.

Claim 8

A digital convergence apparatus, comprising: a first memory storing convergence correction data for a plurality of correction executing points aligned in horizontal or vertical direction on a screen; a static convergence data memory storing a static convergence correction data for correcting the entire screen in the same direction; an offset data memory storing a first offset data for an odd field and a second offset data for an even field, the first and second offset data being used to offset the static convergence correction data, second offset data being based on a distance between scanning lines; selecting means for producing selected output by selectively reading the first or the second offset data stored in the offset data memory according to the odd field period or the even field period; adding means for generating added output by correcting the static convergence correction data stored in the static convergence data memory based on the selected output and adding the corrected static convergence correction data to the convergence correction data stored in the first memory; vertical interpolating means for generating vertical interpolated output by interpolating the added output in the vertical direction; and a convergence correction coil correcting convergence based on the vertical interpolated output.

Claim 9

A digital convergence apparatus as claimed in claim 5, wherein the static convergence correction data stored in the static convergence data memory corresponds with an upper bit of the convergence correction data stored in the first memory; and the first and second offset data stored in the offset data memory correspond with lower bits of the convergence correction data stored in the first memory.

Claim 10

A digital convergence apparatus as claimed in claim 5, wherein the offset memory also stores a third offset data and a fourth offset data, the third and fourth offset data being respectively associated with the even and odd fields and being used to offset the static convergence correction data, at least one of the third and fourth offset data being based on the distance between the scanning lines.

Claim 11

A digital convergence apparatus as claimed in claim 5, wherein the offset data memory stores a plurality of the first offset data for the odd field and a plurality of the second offset data for the even field, the first and second offset data being used to offset the static convergence correction data according to positions on the screen, at least one of the offset data being based on the distance between the scanning lines.

Claim 12

A digital convergence apparatus, comprising: a first memory storing convergence correction data for plural correction executing points aligned in a horizontal or vertical direction on a screen; a first static convergence compensation data memory storing a first static convergence compensation data for correcting the entire screen in the same direction; a second static convergence compensation data memory storing a second static convergence compensation data which is different from the first static convergence compensation data by an amount based on a distance between scanning lines; a selector circuit producing a selected output by selecting an output from the first or the second static convergence compensation data memory in response to an odd field period or an even field period; an adder generating an added output by adding output from the first memory and the selected output; a vertical interpolator generating vertical interpolated output by interpolating the added output in the vertical direction; a convergence correction coil correcting convergence based on the vertical interpolated output.

Claim 13

A digital convergence apparatus, comprising: a first memory storing convergence correction data for plural correction executing points aligned in a horizontal or vertical direction on a screen; a first static convergence compensation data memory storing a first static convergence compensation data for correcting the entire screen in the same direction; a second static convergence compensation data memory storing a second static convergence compensation data which is different from the first static convergence compensation data by an amount based on a distance between scanning lines; a selector circuit producing a selected output by selecting an output from the first or the second static convergence compensation data memory in response to an odd field period or an even field period; an adder generating an added output by adding output from the first memory and the selected output; a vertical interpolator generating vertical interpolated output by interpolating the added output in the vertical direction; a convergence correction coil correcting convergence based on the vertical interpolated output.

Claim 14

A digital convergence apparatus as claimed in claim 9, wherein the convergence correction data stored in the first memory, the first static convergence compensation data and the second static convergence compensation data include data assigned for correcting the convergence in the horizontal and vertical directions of the screen, and the convergence correction coil includes coils that are used to perform convergence corrections in the horizontal and vertical directions of the screen, respectively.

Claim 15

A digital convergence apparatus of claim 9, wherein the convergence correction data stored in the first memory comprises convergence compensation data assigned to the correction executing points on a prescribed horizontal scanning line and differential data between the convergence compensation data of the correction executing points which are mutually adjacent in the vertical direction.

Claim 16

A digital convergence apparatus comprising: a horizontal convergence compensation data memory storing horizontal convergence compensation data for a plurality of correction executing points, the horizontal convergence compensation data for correcting convergence in the horizontal direction on a screen; a vertical convergence compensation data memory storing vertical convergence compensation data for the plurality of correction executing points, the vertical convergence compensation data for correcting convergence in the vertical direction on the screen; a horizontal static convergence compensation data memory storing a horizontal static convergence compensation data for correcting convergence in the horizontal direction on the entire screen; a first static convergence compensation data memory storing a first static convergence compensation data for correcting convergence on the entire screen in the vertical direction; a second static convergence compensation data memory storing a second static convergence compensation data that is different from the first static convergence compensation data by an amount based on a distance between scanning lines; an address controller controlling readout from the horizontal and vertical convergence compensation data memories; a selector circuit producing a selected output by selecting an output from the first or the second static convergence compensation data memory in response to an odd field period or an even field period; horizontal adder generating a horizontal output by adding the horizontal convergence compensation data stored in the horizontal convergence compensation data memory with the horizontal static convergence compensation data; vertical adder generating a vertical output by adding the vertical convergence compensation data stored in the vertical convergence compensation data memory with the selected output from the selector circuit; horizontal interpolator generating a horizontal interpolated output by calculating a convergence compensation data at a prescribed position between horizontally adjacent correction executing points based on the horizontal added output; vertical interpolator generating a vertical interpolated output by calculating a convergence compensation data at a prescribed position between vertically adjacent correction executing points based on the vertical added output; a horizontal convergence correction coil to which the horizontal interpolated output is supplied; and a vertical convergence correction coil to which the vertical interpolated output is supplied.

Claim 17

A digital convergence apparatus comprising: a horizontal convergence compensation data memory storing horizontal convergence compensation data for a plurality of correction executing points, the horizontal convergence compensation data for correcting convergence in the horizontal direction on a screen; a vertical convergence compensation data memory storing vertical convergence compensation data for the plurality of correction executing points, the vertical convergence compensation data for correcting convergence in the vertical direction on the screen; a horizontal static convergence compensation data memory storing a horizontal static convergence compensation data for correcting convergence in the horizontal direction on the entire screen; a first static convergence compensation data memory storing a first static convergence compensation data for correcting convergence on the entire screen in the vertical direction; a second static convergence compensation data memory storing a second static convergence compensation data that is different from the first static convergence compensation data by an amount based on a distance between scanning lines; an address controller controlling readout from the horizontal and vertical convergence compensation data memories; a selector circuit producing a selected output by selecting an output from the first or the second static convergence compensation data memory in response to an odd field period or an even field period; horizontal adder generating a horizontal output by adding the horizontal convergence compensation data stored in the horizontal convergence compensation data memory with the horizontal static convergence compensation data; vertical adder generating a vertical output by adding the vertical convergence compensation data stored in the vertical convergence compensation data memory with the selected output from the selector circuit; horizontal interpolator generating a horizontal interpolated output by calculating a convergence compensation data at a prescribed position between horizontally adjacent correction executing points based on the horizontal added output; vertical interpolator generating a vertical interpolated output by calculating a convergence compensation data at a prescribed position between vertically adjacent correction executing points based on the vertical added output; a horizontal convergence correction coil to which the horizontal interpolated output is supplied; and a vertical convergence correction coil to which the vertical interpolated output is supplied.

Claim 18

A digital convergence apparatus, comprising: a first memory storing convergence correction data for a plurality of correction executing points aligned in a horizontal or vertical direction on a screen; a static convergence data memory storing a static convergence correction data for correcting the entire screen in the same direction; an offset data memory storing a first offset data for an odd field and a second offset data for an even field, the first and second offset data being used to offset the static convergence correction data, second offset data being based on a distance between scanning lines; a selector producing selected output by selectively reading the first or the second offset data stored in the offset data memory according to the odd field period or the even field period; an adder generating added output by correcting the static convergence correction data stored in the static convergence data memory based on the selected output and adding the corrected static convergence correction data to the convergence correction data stored in the first memory; vertical interpolator generating vertical interpolated output by interpolating the added output in the vertical direction; a convergence correction coil correcting convergence based on the vertical interpolated output.

Claim 19

A digital convergence apparatus, comprising: a first memory storing convergence correction data for a plurality of correction executing points aligned in a horizontal or vertical direction on a screen; a static convergence data memory storing a static convergence correction data for correcting the entire screen in the same direction; an offset data memory storing a first offset data for an odd field and a second offset data for an even field, the first and second offset data being used to offset the static convergence correction data, second offset data being based on a distance between scanning lines; a selector producing selected output by selectively reading the first or the second offset data stored in the offset data memory according to the odd field period or the even field period; an adder generating added output by correcting the static convergence correction data stored in the static convergence data memory based on the selected output and adding the corrected static convergence correction data to the convergence correction data stored in the first memory; vertical interpolator generating vertical interpolated output by interpolating the added output in the vertical direction; a convergence correction coil correcting convergence based on the vertical interpolated output.

Claim 20

A digital convergence apparatus as claimed in claim 13, wherein the static convergence correction data stored in the static convergence data memory corresponds with an upper bit of the convergence correction data stored in the first memory; and the first and second offset data stored in the offset data memory correspond with lower bits of the convergence correction data stored in the first memory.

Claim 21

A digital convergence apparatus as claimed in claim 13, wherein the offset memory also stores a third offset data and a fourth offset data, the third and fourth offset data being respectively associated with the even and odd fields and being used to offset the static convergence correction data, at least one of the third and fourth offset data being based on the distance between the scanning lines.

Claim 22

A digital convergence apparatus as claimed in claim 13, wherein the offset data memory stores a plurality of the first offset data for the odd field and a plurality of the second offset data for the even field, the first and second offset data being used to offset the static convergence correction data according to positions on the screen at least one of the offset data being based on the distance between the scanning lines.