US5592164A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for signal processing
Assignee: Deutsches Zentrum für Luft- und Raumfahrt eV
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Filing: 1994-06-24
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Granted: 1997-01-07
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Expires: 2014-06-24
Abstract
Abstract A circuit arrangement for signal processing of discrete or continuous signals of at least one CCD component, includes a multiplexer which receives the signals for processing and has an output, a pre-amplifier having an input connected to the output of the multiplexer, and further having an output. Two sample and hold circuits are provided that each have an input connected to the output of the pre-amplifier, each of the sample and hold circuits further having an output. An operational amplifier is provided having a non-inverting input connected to the output of a first of the sample and hold circuits, and an inverting input connected to the output of a second of the sample and hold circuits, the operational amplifier further has an output. A digital-analog converter having an output connected to the non-inverting input of the operational amplifier and puts out a correction signal. A multiplying digital-analog converter is provided having a reference input connected to the output of the operational amplifier, the multiplying digital-analog converter further having an output. A third sample and hold circuit has an input connected to the output of the multiplying digital-analog converter, the third sample and hold circuit further having an output. A buffer has an input connected to the output of the third sample and hold circuit, and further has an output connected to the input of an analog-digital converter.
Inventors
- 👤 Stefan Hilbert
- 👤 Bernd Kirchner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:58
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/713; H04N5/00; H04N5/14; H04N25/60; H04N25/63
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
231 words
A circuit arrangement for signal processing of discrete or continuous signals of at least one CCD component, comprising: a multiplexer which receives the signals for processing and has an output; a pre-amplifier having an input connected to the output of the multiplexer, and further having an output; two sample and hold circuits each having an input connected to the output of the pre-amplifier, each of the sample and hold circuits further having an output; an operational amplifier having a non-inverting input connected to the output of a first of the sample and hold circuits and an inverting input connected to the output of a second of the sample and hold circuits, the operational amplifier further having an output; a digital-analog converter having an output connected to the non-inverting input of the operational amplifier and putting out a correction signal to the operational amplifier a multiplying digital-analog converter having a reference input connected to the output of the operational amplifier, the multiplying digital-analog converter further having an output; a third sample and hold circuit having an input connected to the output of the multiplying digital-analog converter, the third sample and hold circuit further having an output; a buffer having an input connected to the output of the third sample and hold circuit, the buffer further having an output; and an analog-digital converter having an input connected to the output of the buffer.
Claim 2
Dependent Claim
231 words
A circuit arrangement for signal processing of discrete or continuous signals of at least one CCD component, comprising: a multiplexer which receives the signals for processing and has an output; a pre-amplifier having an input connected to the output of the multiplexer, and further having an output; two sample and hold circuits each having an input connected to the output of the pre-amplifier, each of the sample and hold circuits further having an output; an operational amplifier having a non-inverting input connected to the output of a first of the sample and hold circuits and an inverting input connected to the output of a second of the sample and hold circuits, the operational amplifier further having an output; a digital-analog converter having an output connected to the non-inverting input of the operational amplifier and putting out a correction signal to the operational amplifier a multiplying digital-analog converter having a reference input connected to the output of the operational amplifier, the multiplying digital-analog converter further having an output; a third sample and hold circuit having an input connected to the output of the multiplying digital-analog converter, the third sample and hold circuit further having an output; a buffer having an input connected to the output of the third sample and hold circuit, the buffer further having an output; and an analog-digital converter having an input connected to the output of the buffer.
Claim 3
Dependent Claim
28 words
A circuit arrangement according to claim 1, and further comprising an internal voltage source adapted to deliver a reference voltage to the analog-digital converter and the digital-analog converter.
Claim 4
Dependent Claim
21 words
A circuit arrangement according to claim 2, and further comprising a second, digital analog converter connected to the internal voltage source.
Claim 5
Dependent Claim
19 words
A circuit arrangement according to claim 3, wherein the second digital-analog converter is adapted to be a test generator.
Claim 6
Dependent Claim
56 words
A circuit arrangement according to claim 1, and further comprising first RC low-pass members connected to the multiplexer, second RC low-pass members connected to the pre-amplifier, third RC low-pass members connected to the third sample and hold circuit, and fourth RC low-pass members connected to the buffer, so as to be decoupled from an operational voltage.
Claim 7
Dependent Claim
37 words
A circuit arrangement according to claim 1, and further comprising a second operational amplifier connected between the output of the multiplying digital-analog converter and the input of the third sample and hold circuit as an I/U converter.
Claim 8
Dependent Claim
42 words
A circuit arrangement according to claim 1, wherein the multiplexer, the pre-amplifier, the three sample and hold circuits, the operational amplifier, the digital-analog converter, the multiplying digital-analog converter, the buffer and the analog-digital converter are disposed in a highly integrated hybrid circuit.
Claim 9
Dependent Claim
34 words
A circuit arrangement according to claim 7, wherein the hybrid circuit includes a plurality of modules in a highly modular fashion, the modules respectively having connections that lead separately out of the hybrid circuit.
Claim 10
Dependent Claim
29 words
A circuit arrangement according to claim 8, wherein the modules are adapted so as to be usable in a total combination, in a partial combination and as individual components.
Claim 11
Dependent Claim
44 words
A circuit arrangement according to claim 7, and further comprising external processor means coupled to the hybrid circuit for at least one of correcting at least one of a digital-analog converter output signal and an operational amplifier output signal, and generating signal process pulses.
Claim 12
Dependent Claim
37 words
A circuit arrangement according to claim 1, wherein the digital-analog converter puts out a direct current line-reference correction signal that contains an offset of a signal channel and a median dark current value of a CCD line.
Claim 13
Dependent Claim
35 words
A circuit arrangement according to claim 1, wherein the digital-analog converter puts out a direct current pixel-referenced correction signal that contains an offset of a signal channel and a dark current value of a pixel.
Claim 14
Dependent Claim
22 words
A circuit arrangement according to claim 1, and further comprising high-speed diodes connected to the analog-digital converter for overvoltage and latchup protection.
Claim 15
Dependent Claim
24 words
A circuit arrangement as defined in claim 1, wherein the circuit arrangement is adapted for real-time processing of signals of a CCD image-taking system.
References Cited (Backward Citations)
US4677422A
Cited
US4896155A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |