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Patent US5590291A successfully refreshed from Google Patents.
US5590291A
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Digital signal processing system for limiting a result to be predetermined bit count
Assignee: Mitsubishi Electric Corp
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Filing: 1993-01-04
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Granted: 1996-12-31
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Expires: 2013-01-04
Abstract
Abstract A video codec (coder-decoder) system inputs consecutively admitted frames of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each block of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.
Inventors
- 👤 Tokumichi Murakami
- 👤 Hideo Ohira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:19
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/42; H04N19/43; H04N19/436; H04N19/50; H04N19/503; H04N19/51; H04N19/533; H04N19/577; H04N19/587; H04N19/30
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
148 words
A digital signal processing system, comprising: an instruction memory for storing microinstructions; an instruction execution control circuit for fetching and decoding said microinstructions from said instruction memory, each of said microinstructions including a data operation instruction and a bit limiting instruction designating a significant bit count; a data memory for storing data; a data operation circuit for performing an operation on data from said data memory, said operation being designated by a decoded microinstruction from said instruction execution control circuit; and a limiting circuit for inputting a result of said operation performed by said data operation circuit, inputting a bit limiting instruction from said instruction execution control unit, physically limiting the number of bits of said result to any integer m designated by the bit limiting instruction of said decoded microinstruction, and outputting the limited result to an output bus with a width of n bits, where m<n.
Claim 2
Dependent Claim
148 words
A digital signal processing system, comprising: an instruction memory for storing microinstructions; an instruction execution control circuit for fetching and decoding said microinstructions from said instruction memory, each of said microinstructions including a data operation instruction and a bit limiting instruction designating a significant bit count; a data memory for storing data; a data operation circuit for performing an operation on data from said data memory, said operation being designated by a decoded microinstruction from said instruction execution control circuit; and a limiting circuit for inputting a result of said operation performed by said data operation circuit, inputting a bit limiting instruction from said instruction execution control unit, physically limiting the number of bits of said result to any integer m designated by the bit limiting instruction of said decoded microinstruction, and outputting the limited result to an output bus with a width of n bits, where m<n.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |