US5590286A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for the pipelining of data during direct memory accesses
Assignee: Sun Microsystems Inc
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Filing: 1993-10-07
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Granted: 1996-12-31
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Expires: 2013-10-07
Abstract
Abstract A method and apparatus for the pipelining of data during direct memory accesses. The processor includes an external bus controller, which receives data transmitted across the external bus from an external device, and forwards the data onto the memory bus for transfer to the memory. Similarly, the bus controller receives data to be written to external device from the memory and transfers it across the external bus to the external device. The bus controller includes logic to detect burst transfers and word alignment to determine the minimum number of words that can be transferred across the memory bus while the data transfer from the external device is ongoing. Therefore, instead of waiting for the entire block of data to be received into the processor before transferring it to the memory, portions of the block transferred, for example, two words at a time, are transferred to the memory, while additional data is being received at the processor. If two words are transferred at a time across the memory bus, then at the end of a block transfer only one additional cycle is required to transfer the last two words of data to the memory. Similarly, for a write operation to the external device, data can be piecewise transferred across the slower external bus as it is received in the bus controller in order to minimize the time required to complete the transfer.
Inventors
- 👤 Peter A. Mehring
- 👤 Cau L. Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
314 words
In a system comprising a processor component coupled to an external bus, and an external device coupled to the external bus, an apparatus for transferring data from the external device across the external bus to main memory coupled to the processor component by a high speed memory bus, said external bus operating at a first clock speed and said memory bus operating at a second clock speed faster than the first clock speed, said apparatus comprising: an external bus controller coupled to the memory bus and the external bus for communicating data between the processor component and the external device coupled to the external bus, said bus controller communicating data across the external bus at the speed of the first clock and communicating data across the memory bus at the speed of the second clock, said external controller comprising; a buffer for temporarily storing data communicated from/to the external device pursuant to a write/read operation to be performed, said data stored in the buffer in accordance with the speed of the second clock, a first communication path for communicating data between the external bus controller and the external bus at the rate of the first clock, a second communication path for causing the communication of data between the buffer and the memory bus at the rate of the second clock, a transfer controller which detects a determined number of words stored in the buffer and causes the completion of the operation with respect to the buffered data while the remaining data to be transferred pursuant to the operation is transferred to the buffer; wherein said external bus controller continues to buffer remaining data of the operation and complete the operation with respect to the buffered data such that delay incurred by waiting for the data to be communicated to the external bus controller prior to transferring the data to complete the operation is minimized.
Claim 2
Dependent Claim
314 words
In a system comprising a processor component coupled to an external bus, and an external device coupled to the external bus, an apparatus for transferring data from the external device across the external bus to main memory coupled to the processor component by a high speed memory bus, said external bus operating at a first clock speed and said memory bus operating at a second clock speed faster than the first clock speed, said apparatus comprising: an external bus controller coupled to the memory bus and the external bus for communicating data between the processor component and the external device coupled to the external bus, said bus controller communicating data across the external bus at the speed of the first clock and communicating data across the memory bus at the speed of the second clock, said external controller comprising; a buffer for temporarily storing data communicated from/to the external device pursuant to a write/read operation to be performed, said data stored in the buffer in accordance with the speed of the second clock, a first communication path for communicating data between the external bus controller and the external bus at the rate of the first clock, a second communication path for causing the communication of data between the buffer and the memory bus at the rate of the second clock, a transfer controller which detects a determined number of words stored in the buffer and causes the completion of the operation with respect to the buffered data while the remaining data to be transferred pursuant to the operation is transferred to the buffer; wherein said external bus controller continues to buffer remaining data of the operation and complete the operation with respect to the buffered data such that delay incurred by waiting for the data to be communicated to the external bus controller prior to transferring the data to complete the operation is minimized.
Claim 3
Dependent Claim
74 words
The apparatus as set forth in claim 1, wherein if said operation is a memory write operation in which data is transferred from the external device and written into main memory, said transfer controller issuing a memory write signal to a memory controller to cause the transfer of the data located in the buffer to the memory when a determined number of words are detected, said memory controller operating at the first clock speed.
Claim 4
Dependent Claim
55 words
The apparatus as set forth in claim 1, wherein if said operation is a memory read operation in which data is transferred from the main memory to the external device, said transfer controller transferring the data located in the buffer across the external bus to the external device at the speed of the first clock.
Claim 5
Dependent Claim
29 words
The apparatus as set forth in claim 1, further comprising an address alignment detector for determining address alignment of data to be transferred between memory and the external device.
Claim 6
Dependent Claim
45 words
The apparatus as set forth in claim 4, wherein the determined number of words stored in the buffer prior to transfer of the data from the buffer to complete the operation with respect to the buffered data is determined according to the address alignment detected.
Claim 7
Dependent Claim
82 words
The apparatus as set forth in claim 2, wherein data is transferred across the external bus in blocks of eight words, one word transferred per clock cycle, said transfer controller issuing a memory write signal to the memory controller when two words are detected to be stored in the buffer; wherein data is transferred to memory as the data is received across the external bus such that only two words are transferred to memory after transfer across the external bus is complete.
Claim 8
Dependent Claim
63 words
The apparatus as set forth in claim 3, wherein data is received from memory and stored in the buffer according to the first clock and a bus transfer to transfer the data across the external bus to the external device is initiated once two words are stored in the buffer, wherein data is transferred to the external device as received in the buffer.
Claim 9
Dependent Claim
254 words
In a system comprising a processor coupled to an external bus, and an external device coupled to the external bus, a method for transferring data between the external device across the external bus and main memory coupled to the processor by a high speed memory bus, said communication pursuant to a write operation to be performed, said external bus operating at a first clock speed and said memory bus operating at a second clock speed faster than the first clock speed of the external bus, said method comprising the steps of: transferring data from the external device to be written to memory across the external bus at the speed of the first clock; temporarily storing data transferred from the external device, said data stored in a buffer in accordance with the speed of the second clock; detecting a determined number of words are stored in the buffer; transferring data from the buffer to the memory across the memory bus at the speed of the second clock to complete the write operation with respect to the determined number of words located in the buffer while remaining data to be transferred pursuant to the operation is stored to the buffer; wherein the remaining data of the operation continues to be temporarily stored in the buffer while the operation is completed with respect to the data stored in the buffer such that delay incurred by waiting for the data to be completely transferred to the processor prior to transferring the data to complete the operation is minimized.
Claim 10
Dependent Claim
254 words
In a system comprising a processor coupled to an external bus, and an external device coupled to the external bus, a method for transferring data between the external device across the external bus and main memory coupled to the processor by a high speed memory bus, said communication pursuant to a write operation to be performed, said external bus operating at a first clock speed and said memory bus operating at a second clock speed faster than the first clock speed of the external bus, said method comprising the steps of: transferring data from the external device to be written to memory across the external bus at the speed of the first clock; temporarily storing data transferred from the external device, said data stored in a buffer in accordance with the speed of the second clock; detecting a determined number of words are stored in the buffer; transferring data from the buffer to the memory across the memory bus at the speed of the second clock to complete the write operation with respect to the determined number of words located in the buffer while remaining data to be transferred pursuant to the operation is stored to the buffer; wherein the remaining data of the operation continues to be temporarily stored in the buffer while the operation is completed with respect to the data stored in the buffer such that delay incurred by waiting for the data to be completely transferred to the processor prior to transferring the data to complete the operation is minimized.
Claim 11
Dependent Claim
21 words
The method as set forth in claim 8, wherein said step of detecting is performed in accordance with the second clock.
Claim 12
Dependent Claim
62 words
The method as set forth in claim 8, wherein said step of transferring data from the buffer to the memory across the memory bus comprises the steps of: issuing a memory write signal for the determined number of words located in the buffer; communicating the determined number of words across the memory bus to the memory; and writing the words into memory.
Claim 13
Dependent Claim
42 words
The method as set forth in claim 8, said method further comprising the steps of: determining address alignment of data to be transferred between the external device and memory; adjusting the determined number of words in accordance with the address alignment determined.
Claim 14
Dependent Claim
77 words
The method as set forth in claim 8, wherein data is transferred across the external bus in blocks of eight words, one word transferred per clock cycle, said step of detecting a determined number of words detects when two words are stored in the buffer; wherein data is transferred to memory as the data is received across the external bus such that only two words are transferred to memory after transfer across the external bus is complete.
Claim 15
Dependent Claim
249 words
In a system comprising a processor coupled to an external bus, and an external device coupled to the external bus, an method for transferring data between the external device across the external bus and main memory coupled to the processor by a high speed memory bus, said communication pursuant to a read operation to be performed, said external bus operating at a first clock speed and said memory bus operating at a second clock speed faster than the first clock speed of the external bus, said method comprising the steps of: transferring data from the memory to be read by the external device across the memory bus at the speed of the second clock; temporarily storing data transferred front the memory, said data stored in a buffer in accordance with the speed of the second clock; detecting a determined number of words are stored in the buffer; transferring data front the buffer to the external device across the external bus, to complete the read operation with respect to the determined number of words located in the buffer while the remaining data to be transferred pursuant to the operation is stored to the buffer; wherein the remaining data of the operation continues to be temporarily stored in the buffer while the operation is completed with respect to the data stored in the buffer such that delay incurred by waiting for the data to be completely transferred to the processor prior to transferring the data to complete the operation is minimized.
Claim 16
Dependent Claim
249 words
In a system comprising a processor coupled to an external bus, and an external device coupled to the external bus, an method for transferring data between the external device across the external bus and main memory coupled to the processor by a high speed memory bus, said communication pursuant to a read operation to be performed, said external bus operating at a first clock speed and said memory bus operating at a second clock speed faster than the first clock speed of the external bus, said method comprising the steps of: transferring data from the memory to be read by the external device across the memory bus at the speed of the second clock; temporarily storing data transferred front the memory, said data stored in a buffer in accordance with the speed of the second clock; detecting a determined number of words are stored in the buffer; transferring data front the buffer to the external device across the external bus, to complete the read operation with respect to the determined number of words located in the buffer while the remaining data to be transferred pursuant to the operation is stored to the buffer; wherein the remaining data of the operation continues to be temporarily stored in the buffer while the operation is completed with respect to the data stored in the buffer such that delay incurred by waiting for the data to be completely transferred to the processor prior to transferring the data to complete the operation is minimized.
Claim 17
Dependent Claim
21 words
The method as set forth in claim 13, wherein said step of detecting is performed in accordance with the second clock.
Claim 18
Dependent Claim
82 words
The method as set forth in claim 13, wherein said step of transferring data from the buffer to the external device across the external bus comprises the steps of: transferring the determined number of words stored in the buffer to an input/output buffer coupled to the external bus; communicating the determined number of words across the external bus from the input/output buffer at the next occurrence of the first clock; and latching the words at the external device from the external bus.
Claim 19
Dependent Claim
42 words
The method as set forth in claim 13, said method further comprising the steps of: determining address alignment of data to be transferred between the external device and memory; adjusting the determined number of words in accordance with the address alignment determined.
Claim 20
Dependent Claim
45 words
The method as set forth in claim 13, wherein data is transferred across the external bus in blocks of eight words, one word transferred per clock cycle, said step of detecting a determined number of words detects when two words are stored in the buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |