Address transition detection (ATD) circuit

Claim 2

An address transition detection (ATD) circuit for use in a memory, comprising: input means for receiving an address signal; discharging means for providing a discharge path from a first node to a first voltage reference node for a first time period in response to a change in state of the address signal; charging means for providing a charging path from a second voltage reference node to a second node for a second time period in response to a change in state of the address signal; and load means for accelerating discharging of the first node by turning off in response to charging of the second node and for accelerating charging of the first node in response to expiration of the second time period.

Claim 3

An ATD circuit in accordance with claim 1, wherein the load means comprises: a first p-channel transistor having a drain coupled to the first node, a gate coupled to the second node, and a source coupled to the second voltage reference node.

Claim 4

An ATD circuit in accordance with claim 1, further comprising: output means for generating an output pulse in an output node in response to the first node being discharged; and feedback means for at least partially discharging the second node in response to the output pulse.

Claim 5

An ATD circuit in accordance with claim 3, wherein the feedback means comprises: a first n-channel transistor having a drain coupled to the second node, a gate coupled to the output node, and a source coupled to the first voltage reference node.

Claim 6

An address transition detection (ATD) circuit for use in a memory, comprising: input means for receiving an address signal; first pulse means for generating a first pulse in a first node in response to a change in state of the address signal; second pulse means for generating a second pulse in a second node in response to a change in state of the address signal; and load means, coupled to the first and second nodes, for accelerating assertion of the first pulse in response to assertion of the second pulse and for accelerating deassertion of the first pulse in response to deassertion of the second pulse.

Claim 7

An address transition detection (ATD) circuit for use in a memory, comprising: input means for receiving an address signal; first pulse means for generating a first pulse in a first node in response to a change in state of the address signal; second pulse means for generating a second pulse in a second node in response to a change in state of the address signal; and load means, coupled to the first and second nodes, for accelerating assertion of the first pulse in response to assertion of the second pulse and for accelerating deassertion of the first pulse in response to deassertion of the second pulse.

Claim 8

An ATD circuit in accordance with claim 5, further comprising: output means, coupled to the first node, for generating an output pulse in an output node in response to the first pulse; and feedback means, coupled to the second and output nodes, for preparing the load means to accelerate deassertion of the first pulse in response to the output pulse.

Claim 9

An ATD circuit in accordance with claim 5, wherein the first pulse means comprises: first and second series connected n-channel transistors coupled to provide a discharge path from the first node to a first voltage reference node to generate the first pulse; and delay means, coupled to the second n-channel transistor, for turning the second n-channel transistor on simultaneously with the first n-channel transistor for a first time period equal to a width of the first pulse.

Claim 10

An ATD circuit in accordance with claim 5, wherein the second pulse means comprises: first and second series connected p-channel transistors coupled to provide a charging path from a second voltage reference node to the second node to generate the second pulse; and delay means, coupled to the second p-channel transistor, for turning the second p-channel transistor on simultaneously with the first p-channel transistor for a second time period equal to a width of the second pulse.

Claim 11

An ATD circuit in accordance with claim 8, wherein the delay means comprises an odd number of CMOS inverters coupled to a gate of the second p-channel transistor.

Claim 12

An ATD circuit in accordance with claim 6, wherein the output means comprises: a first logic gate having an inverting function, a first input and an output, the first input being coupled to the first node and the output being coupled to the output node.

Claim 13

An ATD circuit in accordance with claim 10, wherein the first logic gate comprises a NOR gate.

Claim 14

An ATD circuit in accordance with claim 6, wherein the feedback means comprises: a third n-channel transistor having a drain coupled to the second node, a gate coupled to the output node, and a source coupled to a first voltage reference node.

Claim 15

An ATD circuit in accordance with claim 5, wherein the load means comprises: a third p-channel transistor having a drain coupled to the first node, a gate coupled to the second node, and a source coupled to a second voltage reference node.

Claim 16

An ATD circuit in accordance with claim 5, further comprising: pull down means, coupled to the second node, for providing a discharge path from the second node to a first voltage reference node.

Claim 17

An ATD circuit in accordance with claim 14, wherein the pull down means comprises: a fourth n-channel transistor having a drain coupled to the second node, a source coupled to the first voltage reference node, and a gate coupled to a second voltage reference node.

Claim 18

A memory system, comprising: an array of memory cells; input means for receiving a plurality of address signals; decoder means, coupled to the array of memory cells, for decoding the plurality of address signals to select a row and a column of the array of memory cells; a plurality of address cells coupled to the input means so that each address cell receives an associated one of the address signals, each of the address cells including first and second pulse means for generating first and second pulses, respectively, in response to a change in state of the associated address signal; and an output circuit including load means for accelerating assertion of the first pulse generated by any one of the address cells in response to assertion of the second pulse and for accelerating deassertion of the first pulse generated by any one of the address cells in response to deassertion of the second pulse.

Claim 19

A memory system, comprising: an array of memory cells; input means for receiving a plurality of address signals; decoder means, coupled to the array of memory cells, for decoding the plurality of address signals to select a row and a column of the array of memory cells; a plurality of address cells coupled to the input means so that each address cell receives an associated one of the address signals, each of the address cells including first and second pulse means for generating first and second pulses, respectively, in response to a change in state of the associated address signal; and an output circuit including load means for accelerating assertion of the first pulse generated by any one of the address cells in response to assertion of the second pulse and for accelerating deassertion of the first pulse generated by any one of the address cells in response to deassertion of the second pulse.

Claim 20

A memory system in accordance with claim 16, wherein the output circuit comprises: a first node coupled to at least some of the address cells to receive the first pulse; and a second node coupled to at least some of the address cells to receive the second pulse.

Claim 21

A memory system in accordance with claim 16, wherein the output circuit further comprises: output means for generating an output pulse in response to the first pulse generated by any one of the address cells; and feedback means for preparing the load means to accelerate deassertion of the first pulse in response to the output pulse.

Claim 22

A memory system in accordance with claim 17, wherein the first pulse means of each of the address cells comprises: first and second series connected n-channel transistors coupled to provide a discharge path from the first node to a first voltage reference node to generate the first pulse; and delay means, coupled to the second n-channel transistor, for turning the second n-channel transistor on simultaneously with the first n-channel transistor for a first time period equal to a width of the first pulse.

Claim 23

A memory system in accordance with claim 17, wherein the second pulse means of each of the address cells comprises: first and second series connected p-channel transistors coupled to provide a charging path from a second voltage reference node to the second node to generate the second pulse; and delay means, coupled to the second p-channel transistor, for turning the second p-channel transistor on simultaneously with the first p-channel transistor for a second time period equal to a width of the second pulse.

Claim 24

A memory system in accordance with claim 20, wherein the delay means comprises an odd number of CMOS inverters coupled to a gate of the second p-channel transistor.

Claim 25

A memory system in accordance with claim 18, wherein the output means comprises: a first logic gate having an inverting function, a first input and an output, the first input coupled to receive the first pulse generated by any of the address cells.

Claim 26

A memory system in accordance with claim 22, wherein the first logic gate comprises a NOR gate.

Claim 27

A memory system in accordance with claim 18, wherein the feedback means comprises: a third n-channel transistor having a drain coupled to receive the second pulse generated by any of the address cells, a gate coupled to receive the output pulse, and a source coupled to a first voltage reference node.

Claim 28

A memory system in accordance with claim 16, wherein the load means comprises: a third p-channel transistor having a drain coupled to pull up the first pulse generated by any of the address cells, a gate coupled to receive the second pulse generated by any of the address cells, and a source coupled to a second voltage reference node.

Claim 31

A method in accordance with claim 26, wherein step (e) comprises the step of: at least partially discharging the second node with a first n-channel transistor having a gate coupled to the output node.

Claim 32

A method in accordance with claim 26, wherein step (f) comprises the step of: charging the first node with a first p-channel transistor having a gate coupled to the second node.

Claim 33

An address transition detection (ATD) circuit for use in a memory, comprising: an input circuit which receives an address signal; a discharging circuit coupled to the input circuit which completes a discharge path from a first node to a first voltage reference node for a first time period in response to a change in state of the address signal; a charging circuit coupled to the discharge circuit which completes a charging path from a second voltage reference node to a second node for a second time period in response to a change in state of the address signal; and a load circuit coupled to the first and second nodes which accelerates discharging of the first node by turning off in response to charging of the second node and which accelerates charging of the first node in response to expiration of the second time period.

Claim 34

An address transition detection (ATD) circuit for use in a memory, comprising: an input circuit which receives an address signal; a discharging circuit coupled to the input circuit which completes a discharge path from a first node to a first voltage reference node for a first time period in response to a change in state of the address signal; a charging circuit coupled to the discharge circuit which completes a charging path from a second voltage reference node to a second node for a second time period in response to a change in state of the address signal; and a load circuit coupled to the first and second nodes which accelerates discharging of the first node by turning off in response to charging of the second node and which accelerates charging of the first node in response to expiration of the second time period.

Claim 35

An ATD circuit in accordance with claim 29, wherein the load circuit comprises: a first p-channel transistor having a drain coupled to the first node, a gate coupled to the second node, and a source coupled to the second voltage reference node.

Claim 36

An ATD circuit in accordance with claim 29, further comprising: an output circuit which generates an output pulse in an output node in response to the first node being discharged; and a feedback circuit which at least partially discharges the second node in response to the output pulse.

Claim 37

An ATD circuit in accordance with claim 31, wherein the feedback circuit comprises: a first n-channel transistor having a drain coupled to the second node, a gate coupled to the output node, and a source coupled to the first voltage reference node.

Claim 38

An address transition detection (ATD) circuit for use in a memory, comprising: an input circuit which receives an address signal; a first pulse generator which generates a first pulse in a first node in response to a change in state of the address signal; a second pulse generator which generates a second pulse in a second node in response to a change in state of the address signal; and a load circuit, coupled to the first and second nodes, which accelerates assertion of the first pulse in response to assertion of the second pulse and which accelerates deassertion of the first pulse in response to deassertion of the second pulse.

Claim 39

An address transition detection (ATD) circuit for use in a memory, comprising: an input circuit which receives an address signal; a first pulse generator which generates a first pulse in a first node in response to a change in state of the address signal; a second pulse generator which generates a second pulse in a second node in response to a change in state of the address signal; and a load circuit, coupled to the first and second nodes, which accelerates assertion of the first pulse in response to assertion of the second pulse and which accelerates deassertion of the first pulse in response to deassertion of the second pulse.

Claim 40

An ATD circuit in accordance with claim 33, further comprising: an output circuit, coupled to the first node, which generates an output pulse in an output node in response to the first pulse; and a feedback circuit, coupled to the second and output nodes, which prepares the load means to accelerate deassertion of the first pulse in response to the output pulse.

Claim 41

An ATD circuit in accordance with claim 33, wherein the first pulse generator comprises: first and second series connected n-channel transistors coupled to provide a discharge path from the first node to a first voltage reference node to generate the first pulse; and a delay circuit, coupled to the second n-channel transistor, which turns the second n-channel transistor on simultaneously with the first n-channel transistor for a first time period equal to a width of the first pulse.

Claim 42

An ATD circuit in accordance with claim 33, wherein the second pulse generator comprises: first and second series connected p-channel transistors coupled to provide a charging path from a second voltage reference node to the second node to generate the second pulse; and a delay circuit, coupled to the second p-channel transistor, which turns the second p-channel transistor on simultaneously with the first p-channel transistor for a second time period equal to a width of the second pulse.

Claim 43

An ATD circuit in accordance with claim 36, wherein the delay circuit comprises an odd number of CMOS inverters coupled to a gate of the second p-channel transistor.

Claim 46

A method in accordance with claim 38, further comprising the step of: generating an output pulse in an output node in response to the step of discharging the first node; and feeding the output pulse back to be used to prepare for charging of the first node.

Claim 47

A method in accordance with claim 39, wherein the feeding step comprises the step of: at least partially discharging the second node with a first n-channel transistor having a gate coupled to the output node.

Claim 48

A method in accordance with claim 38, wherein the step of accelerating charging of the first node comprises the step of: charging the first node with a first p-channel transistor having a gate coupled to the second node.