Circuit and method for retaining DRAM content

Claim 2

A memory control circuit comprising a DRAM, a drive circuit for driving said DRAM, a DRAM control circuit for controlling operation of said DRAM through said drive circuit, a power supply connected to said DRAM, said DRAM control circuit and said drive circuit, a first detection circuit for generating a first detection signal that is output to said DRAM control circuit when the power supply voltage is lowered to a first predetermined voltage, and a second detection circuit for generating a second detection signal that is output to said drive circuit when the power supply voltage is lowered to a second predetermined voltage lower than said first predetermined voltage, wherein said DRAM control circuit, when said first detection signal is received, starts self-refreshing and, when said second detection signal is received, said drive circuit establishes a self-refresh mode for said DRAM.

Claim 3

A memory control circuit according to claim 1, further including an auxiliary power supply that is connected to said drive circuit and said DRAM for providing power thereto after said power supply is cut off in order to provide sufficient power for maintaining said established self-refresh mode.

Claim 4

A memory control circuit according to claim 2, wherein said power supply is connected to said DRAM and said drive circuit through a power line having a first diode and wherein said auxilliary power supply is connected to said power line between said first diode and said DRAM and said drive circuit through a second diode for switching between supplying power from said power supply to supplying power from said auxilliary power supply over said power line.

Claim 5

A memory control circuit according to claim 1, wherein said drive circuit has an output circuit having a first impedance value when driving said DRAM that includes RAS and CAS output signals for controlling said DRAM, said RAS and CAS signals being connected to a pull down circuit, wherein when said second detection signal is received, said output circuit is switched from said first impedance value to a second impedance value higher than said first impedance value for pulling low said RAS and CAS signals with said pull down circuit to set the self refresh mode.

Claim 6

A memory control circuit according to claim 4, wherein said drive circuit includes an enable pin that receives said second detection signal for controlling the switching of the output circuit between said first and second impedance values.

Claim 7

A memory control circuit according to claim 2, further comprising a power line connecting said DRAM control circuit through a power line to said power supply, and a capacitor connected to said power line in parallel with said power supply.

Claim 8

A memory control circuit according to claim 6, wherein said first detection signal is connected to said power supply through a first diode, said power line is connected to said main power supply through a second diode, said DRAM and said drive circuit are connected to said to said power supply by another power line through a third diode and said auxiliary power supply is connected to said another power line between said third diode and said DRAM and said drive circuit through a fourth diode.

Claim 9

A memory control circuit, comprising: a main circuit, a DRAM, a drive circuit for driving said DRAM, a DRAM control circuit for controlling operation of said DRAM through said drive circuit, a first power supply supplying a power supply voltage to said main circuit, said DRAM, said DRAM control circuit and said drive circuit, a first detection circuit connected to said first power supply for monitoring the supply voltage and for generating a first detection signal that is output to said DRAM control circuit when the power supply voltage decreases below a first predetermined voltage, and a second detection circuit for generating a second detection signal that is output to said drive circuit when the power supply voltage is lowered to a second predetermined voltage lower than said first predetermined voltage, wherein said DRAM control circuit, when said first detection signal is received, stops data transfer and starts self-refreshing of said DRAM after completion of data transfer, means responsive to said second detection signal being received by said drive circuit for setting a self-refresh mode for said DRAM, and a second auxilliary power supply that is connected to said drive circuit and said DRAM for providing power thereto after said power supply voltage is cut off in order to provide sufficient power for maintaining said self-refresh mode.

Claim 10

A memory control circuit, comprising: a main circuit, a DRAM, a drive circuit for driving said DRAM, a DRAM control circuit for controlling operation of said DRAM through said drive circuit, a first power supply supplying a power supply voltage to said main circuit, said DRAM, said DRAM control circuit and said drive circuit, a first detection circuit connected to said first power supply for monitoring the supply voltage and for generating a first detection signal that is output to said DRAM control circuit when the power supply voltage decreases below a first predetermined voltage, and a second detection circuit for generating a second detection signal that is output to said drive circuit when the power supply voltage is lowered to a second predetermined voltage lower than said first predetermined voltage, wherein said DRAM control circuit, when said first detection signal is received, stops data transfer and starts self-refreshing of said DRAM after completion of data transfer, means responsive to said second detection signal being received by said drive circuit for setting a self-refresh mode for said DRAM, and a second auxilliary power supply that is connected to said drive circuit and said DRAM for providing power thereto after said power supply voltage is cut off in order to provide sufficient power for maintaining said self-refresh mode.

Claim 11

A memory control circuit according to claim 8, wherein said self-refresh mode setting means comprises said drive circuit having an output circuit having a first impedance value when driving said DRAM that includes RAS and CAS output signals for controlling said DRAM and said RAS and CAS signals being connected to a pull down circuit, wherein when said second detection signal is received, said output circuit is switched from said first impedance value to a second impedance value higher than said first impedance value for pulling low said RAS and CAS signals with said pull down circuit to set the self refresh mode.

Claim 12

A memory control circuit according to claim 9, wherein said drive circuit includes an enable pin that receives said second detection signal for controlling the switching of the output circuit between said first and second impedance values.

Claim 13

A memory control circuit according to claim 8, further comprising said DRAM having a data through rate (Tsr) and a data transfer rate (Ttr), a minimum voltage level V1 supplied by said first power supply, a voltage value V2 and a voltage value V3 that is a minimum voltage at which data transfer can be completed, wherein V2=V3+(Ttr/Tsr) and said first predetermined voltage ranges between V1 and V2.

Claim 14

A memory control circuit according to claim 11, further comprising said drive circuit performing said stop of data transfer and start of self-refreshing of said DRAM in elapsed time Tb, a minimum voltage level V5 at which said DRAM control circuit still functions correctly and a voltage level V4, wherein V4=Vt1-(Ttr+Tb)/Tsr and said second predetermined voltage ranges between V4 and V5.

Claim 15

A memory control circuit according to claim 12, wherein a minimum difference between said first and second predetermined voltages is at least 1 nanovolt.

Claim 16

A memory module circuit, comprising: a DRAM having a self refresh mode, a power supply line connected to said DRAM and to a drive circuit for driving said DRAM, said drive circuit including: an output circuit which has a first impedance value during driving of said DRAM and a second impedance value, RAS and CAS output signals for controlling said DRAM, the RAS and CAS signals being connected to said DRAM, and an enable pin that receives an input signal for pulling low said RAS and CAS signals to establish said self refresh mode.

Claim 17

A memory module circuit, comprising: a DRAM having a self refresh mode, a power supply line connected to said DRAM and to a drive circuit for driving said DRAM, said drive circuit including: an output circuit which has a first impedance value during driving of said DRAM and a second impedance value, RAS and CAS output signals for controlling said DRAM, the RAS and CAS signals being connected to said DRAM, and an enable pin that receives an input signal for pulling low said RAS and CAS signals to establish said self refresh mode.

Claim 18

A memory module circuit according to claim 14, wherein: said second impedance value is higher than said first impedance value, and said enable pin controls switching of said output circuit between said first and said second impedance values to establish said self refresh mode.

Claim 19

A memory module circuit, comprising: a DRAM having a self refresh mode, a pull down circuit, a power supply line connected to said DRAM and a drive circuit for driving said DRAM, an output circuit which has a first impedance value during driving said DRAM and a second impedance value, RAS and CAS output signals for controlling said DRAM, the RAS and CAS signals being connected to said DRAM, and an enable pin that receives an input signal for pulling low said RAS and CAS signals to establish said self refresh mode.

Claim 20

A memory module circuit, comprising: a DRAM having a self refresh mode, a pull down circuit, a power supply line connected to said DRAM and a drive circuit for driving said DRAM, an output circuit which has a first impedance value during driving said DRAM and a second impedance value, RAS and CAS output signals for controlling said DRAM, the RAS and CAS signals being connected to said DRAM, and an enable pin that receives an input signal for pulling low said RAS and CAS signals to establish said self refresh mode.

Claim 21

A memory module circuit according to claim 16, wherein: said second impedance value is higher than said first impedance value, and said enable pin controls switching of said output circuit between said first and said second impedance values to establish said self refresh mode.

Claim 22

A memory module circuit according to claim 16, wherein said pull down circuit is connected to said RAS and CAS output signals between said drive circuit and said DRAM for pulling low said RAS and CAS signals in response to said input signal being received at said enable pin.