Patent US5590072A successfully refreshed from Google Patents.
US5590072A
Expired / Lapsed
US
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Nonvolatile semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-05-04
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Granted: 1996-12-31
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Expires: 2015-05-04
Abstract
Abstract An electrically erasable and programmable read only memory device includes a first select device and a NAND cell string consisting of a plurality or memory transistors. Each memory transistor has a floating gate separated by a tunnel oxide layer from a channel region formed on a semiconductor substrate and a control gate separated by an interlayer insulation layer from the floating gate. Respective channels of the memory transistors are serially connected to each other by source-drain regions. The control gate is connected to a corresponding word line. The first select device connects one terminal of the NAND cell string to a corresponding bit line. A resistor having a preset resistance value is connected between the first select device and a bit line. An amplifying device amplifies current flowing through the NAND cell string and supplies the amplified current to the bit line.
Inventors
- 👤 Jeong-Hyuk Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:38
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/04; G11C16/0483; G11C5/00; G11C5/02; G11C5/025; H; H10; H10B; H10B41/00; H10B41/30; H10B41/35; H10B69/00; H10D; H10D84/00; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
178 words
A connecting device within an electrically erasable and programmable read only memory device having a NAND cell string and first select means, said NAND cell string including a plurality of memory transistors, each of said memory transistors having a floating gate separated by a tunnel oxide layer from a channel region formed on a semiconductor substrate, and each of said memory transistors having a control gate separated by an interlayer insulation layer from said floating gate, respective channels of said memory transistors being serially connected to each other by source-drain regions, said control gate of each of said memory transistors being respectively connected to a corresponding word line, said first select means connected to one terminal of said NAND cell string, said device comprising: a resistor connected between said first select means and a bit line, said resistor having a preset resistance value; and an amplifying device connected between said first select means and said bit line which amplifies a reading current flowing through said NAND cell string and which supplies the amplified current to said bit line.
Claim 2
Dependent Claim
178 words
A connecting device within an electrically erasable and programmable read only memory device having a NAND cell string and first select means, said NAND cell string including a plurality of memory transistors, each of said memory transistors having a floating gate separated by a tunnel oxide layer from a channel region formed on a semiconductor substrate, and each of said memory transistors having a control gate separated by an interlayer insulation layer from said floating gate, respective channels of said memory transistors being serially connected to each other by source-drain regions, said control gate of each of said memory transistors being respectively connected to a corresponding word line, said first select means connected to one terminal of said NAND cell string, said device comprising: a resistor connected between said first select means and a bit line, said resistor having a preset resistance value; and an amplifying device connected between said first select means and said bit line which amplifies a reading current flowing through said NAND cell string and which supplies the amplified current to said bit line.
Claim 3
Dependent Claim
51 words
A connecting device within an electrically erasable and programmable read only memory device as set forth in claim 1, wherein said amplifying device is a bipolar transistor having an emitter connected to said bit line, a collector connected to a ground terminal and a base connected to said first select means.
Claim 4
Dependent Claim
171 words
An electrically erasable and programmable read only memory device comprising: a semiconductor substrate; a well of a first conductivity type formed on said semiconductor substrate; a predetermined number of memory transistors, each of said memory transistors having: a channel formed on said well; a floating gate separated by a first insulation layer from said channel region; a control gate separated by an interlayer insulation layer from said floating gate; and source-drain regions of a second conductivity type adjacent to said channel, middle portions of said source-drain regions having an impurity concentration level higher than portions overlapped by said floating gate, said channels of said memory transistors being serially connected to each other by said source-drain regions, said control gate of each of said memory transistors being respectively connected to a corresponding word line; and a select transistor having a channel connected between one terminal of the serially connected channels of said memory transistors and a bit line, and having a gate separated by a gate insulation layer from a channel region.
Claim 5
Dependent Claim
171 words
An electrically erasable and programmable read only memory device comprising: a semiconductor substrate; a well of a first conductivity type formed on said semiconductor substrate; a predetermined number of memory transistors, each of said memory transistors having: a channel formed on said well; a floating gate separated by a first insulation layer from said channel region; a control gate separated by an interlayer insulation layer from said floating gate; and source-drain regions of a second conductivity type adjacent to said channel, middle portions of said source-drain regions having an impurity concentration level higher than portions overlapped by said floating gate, said channels of said memory transistors being serially connected to each other by said source-drain regions, said control gate of each of said memory transistors being respectively connected to a corresponding word line; and a select transistor having a channel connected between one terminal of the serially connected channels of said memory transistors and a bit line, and having a gate separated by a gate insulation layer from a channel region.
Claim 6
Dependent Claim
71 words
An electrically erasable and programmable read only memory device as set forth in claim 3, wherein a drain of said select transistor is connected to a base region of said second conductivity type, said base region being connected to said bit line through a resistor contact of said second conductivity type and an emitter contact of said first conductivity type, said resistor contact and said emitter contact being connected in parallel.
Claim 7
Dependent Claim
85 words
An electrically erasable and programmable read only memory device as set forth in claim 3, wherein a drain of said select transistor is connected to a base region of said second conductivity type, said base region being connected to a resistor contact of said second conductivity type and an emitter contact of said first conductivity type, said emitter contact enclosing said resistor contact and being separated from said resistor contact by an insulation layer, said resistor contact and said emitter contact being connected in parallel.
References Cited (Backward Citations)
US4903236A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |