Sensor drive circuit

Claim 2

A sensor drive circuit comprising: a reference sensor having first and second ends and including a first coil of a fixed inductance; a variable sensor including a second coil of a variable inductance, said second coil being connected in series with said first coil; amplitude control means receiving a first signal from a side of the first end of said reference sensor and a second signal from a side of the second end thereof for controlling an amplitude of a difference signal between said first and second signals so as to be held constant; and inductance detection signal output means for outputting an inductance detection signal responsive to the amount of variation in the inductance of said second coil of said variable sensor, said amplitude control means including: peak detecting means receiving said first and second signals for detecting a peak value of said difference signal to output a peak detection signal; and signal applying means receiving said peak detection signal for applying a signal to said first and second coils so that amplitudes of said first and second signals are varied in response to said peak detection signal.

Claim 3

The sensor drive circuit of claim 1, wherein said peak detecting means includes: subtraction means for performing subtraction of said first and second signal to output said difference signal; peak hold means for detecting the peak value of said difference signal and holding said value to output a peak signal; and sampling means for sampling said peak signal during a predetermined sampling time period to output said peak detection signal, said sensor drive circuit further comprising: reset signal generating means receiving a reset time period control signal for varying an activation timing to output a reset signal in response to a cycle of said reset time period control signal; and reset executing means for setting the peak value of said difference signal held by said peak hold means to a predetermined initial level when said reset signal is active.

Claim 4

The sensor drive circuit of claim 1, wherein said peak detecting means detects a positive peak value and a negative peak value of said difference signal, and said peak detection signal is a difference between said positive peak value and said negative peak value.

Claim 5

The sensor drive circuit of claim 1, wherein the second end of said reference sensor is connected to a first end of said variable sensor; said first signal is provided at the first end of said reference sensor; said second signal is provided at a second end of said variable sensor; and said inductance detection signal output means includes second peak detecting means receiving a third signal provided at the first end of said variable sensor for detecting a peak value of a difference signal between said third signal and a ground level to output said peak value as said inductance detection signal.

Claim 6

The sensor drive circuit of claim 1, wherein the second end of said reference sensor is connected to a first end of said variable sensor, and said signal applying means includes: amplitude control signal output means receiving said peak detection signal and a reference voltage for outputting an amplitude control signal on the basis of a result of comparison between said peak detection signal and said reference voltage; variable amplitude means for determining an amplitude to output a variable-amplitude signal in response to said amplitude control signal; and signal providing means for providing said variable-amplitude signal to the first end of said reference coil and providing an inverted signal of said variable-amplitude signal to a second end of said variable coil.

Claim 7

The sensor drive circuit of claim 5, wherein said first signal is provided at the first end of said reference sensor; said second signal is provided at the second end of said variable sensor; and said inductance detection signal output means includes: voltage dividing means for dividing a voltage of said amplitude control signal to output a voltage-divided signal; amplifying means receiving a third signal provided at the first end of said variable sensor and said voltage-divided signal for outputting an amplified signal of a difference between said voltage-divided signal and said third signal; and signal processing means for performing signal processing upon said amplified signal to output said inductance detection signal.

Claim 8

The sensor drive circuit of claim 6, wherein said signal processing means includes second peak detecting means for detecting a peak value of said amplified signal to output said peak value as said inductance detection signal.

Claim 9

The sensor drive circuit of claim 6, wherein said signal processing means includes: full-wave rectifying means for full-wave rectifying said amplified signal to output a rectified signal; and integration means for integrating said rectified signal to output a resultant signal as said inductance detection signal.

Claim 10

The sensor drive circuit of claim 5, wherein said variable amplitude means includes variable peak value means for determining a peak value in response to said amplitude control signal to output a rectangular-wave signal of said peak value as said variable-amplitude signal.

Claim 11

The sensor drive circuit of claim 1, wherein said inductance detection signal output means includes second peak detecting means receiving a third signal provided at a first end of said variable sensor and a fourth signal provided at a second end thereof for detecting a peak value of a difference signal between said third and fourth signals to output said peak value as said inductance detection signal.

Claim 12

The sensor drive circuit of claim 10, wherein said peak detecting means includes: subtraction means for performing subtraction of said first and second signals to output said difference signal; peak hold means for detecting the peak value of said difference signal and holding said value to output a peak signal; and sampling means for sampling said peak signal during a predetermined sampling time period to output said peak detection signal.

Claim 13

The sensor drive circuit of claim 11, wherein said peak hold means includes: a first operational amplifier having a positive input receiving said difference signal; a diode having an anode connected to an output of said first operational amplifier; a second operational amplifier having a positive input connected to a cathode of said diode, and an output fed back to a negative input of said second operational amplifier and a negative input of said first operational amplifier; and a capacitor having a first electrode connected to the positive input of said second operational amplifier, and a second electrode grounded, the output of said second operational amplifier being specified as said peak signal.

Claim 14

The sensor drive circuit of claim 12, wherein said peak hold means further includes switching means receiving an external reset signal for controlling connection/disconnection between the positive input of said second operational amplifier and a ground level in response to said reset signal.

Claim 15

The sensor drive circuit of claim 12, wherein said peak hold means further includes a resistor having a first end connected to the first electrode of said capacitor, and a second end grounded.

Claim 16

The sensor drive circuit of claim 12, wherein said peak hold means further includes: a resistor having a first end connected to the first electrode of said capacitor; and switching means receiving an external reset signal for controlling connection/disconnection between a second end of said resistor and a ground level in response to said reset signal.

Claim 17

The sensor drive circuit of claim 10, wherein said peak detecting means includes: subtraction means for performing subtraction of said first and second signals to output said difference signal; A/D converting means for analog-to-digital converting said difference signal to output a digital difference signal; digital peak value detecting means receiving said digital difference signal for detecting a peak value of said digital difference signal during a predetermined sampling time period to output a digital peak signal; and D/A converting means for digital-to-analog converting said digital peak signal to output said peak detection signal.

Claim 18

The sensor drive circuit of claim 10, wherein the second end of said reference sensor is connected to the first end of said variable sensor; said first and third signals are provided at the first end of said reference sensor; said second signal is provided at the second end of said reference sensor; and said fourth signal is provided at the second end of said variable sensor.

Claim 19

The sensor drive circuit of claim 10, wherein the second end of said reference sensor is connected to the first end of said variable sensor; said first signal is provided at the first end of said reference sensor; said second and fourth signals are provided at the second end of said variable sensor; and said third signal is provided at the first end of said variable sensor.

Claim 20

The sensor drive circuit of claim 10, wherein said peak detecting means includes: subtraction means for performing subtraction of said first and second signals to output said difference signal; peak hold means for detecting the peak value of said difference signal and holding said value to output a peak signal; and sampling means for sampling said peak signal during a predetermined sampling time period to output said peak detection signal, said sensor drive circuit further comprising: reset signal generating means receiving a reset time period control signal for varying an activation timing to output a reset signal in response to a cycle of said reset time period control signal; and reset executing means for setting the peak value of said difference signal held by said peak hold means to a predetermined initial level when said reset signal is active.

Claim 21

The sensor drive circuit of claim 19, wherein said reset signal generating means includes: a comparator having a first input receiving said reset time period control signal and a second input receiving a constant voltage for outputting a comparison result signal; frequency dividing means for dividing a frequency of said comparison result signal to output a frequency-divided signal; and differentiation means for differentiating said frequency-divided signal to output said reset signal.

Claim 22

The sensor drive circuit of claim 10, wherein said peak detecting means detects a positive peak value and a negative peak value of said difference signal, and said peak detection signal is a difference between said positive peak value and said negative peak value.

Claim 23

The sensor drive circuit of claim 21, wherein said peak detecting means includes: peak-to-peak hold means for detecting a peak-to-peak value and holding said value to output a peak-to-peak signal, said peak-to-peak value being a difference between a positive peak value of said first signal and a negative peak value of said second signal; and sampling means for sampling said peak-to-peak signal during a predetermined sampling time period to output said peak detection signal.

Claim 24

The sensor drive circuit of claim 22, wherein said peak-to-peak hold means includes: a first diode having an anode receiving said first signal; a first capacitor having a first electrode connected to a cathode of said first diode, and a second electrode receiving said second signal; a second diode having a cathode connected to the anode of said first diode; a second capacitor having a first electrode connected to the second electrode of said first capacitor, and a second electrode connected to an anode of said second diode: and subtraction means for performing subtraction of a first voltage provided at the first electrode of said first capacitor and a second voltage provided at the second electrode of said second capacitor to output said peak-to-peak signal.

Claim 25

The sensor drive circuit of claim 22, wherein said peak-to-peak hold means includes: a first operational amplifier having a positive input receiving said first signal; a first diode having an anode receiving an output of said first operational amplifier; a first capacitor having a first electrode connected to a cathode of said first diode, and a second electrode grounded; a second operational amplifier having a positive input connected to the cathode of said first diode, and an output ted back to a negative input of said second operational amplifier and a negative input of said first operational amplifier; a third operational amplifier having a positive input receiving said second signal; a second diode having a cathode connected to said third operational amplifier; a second capacitor having a first electrode connected to an anode of said second diode, and a second electrode grounded; a fourth operational amplifier having a positive input connected to the anode of said second diode, and an output fed back to a negative input of said fourth operational amplifier and a negative input of said third operational amplifier; and subtraction means for performing subtraction of a first voltage provided at the output of said second operational amplifier and a second voltage provided at the output of said fourth operational amplifier to output said peak-to-peak signal.