US5588112A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DMA controller for memory scrubbing
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-02-20
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Granted: 1996-12-24
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Expires: 2016-02-20
Abstract
Abstract A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data is stored by the direct memory access controller, the check bit data is used by the direct memroy access controller to correct the error, and the corrected data element is rewritten to the original storage address. By the use of this arrangement, the central processing unit or units of the computer system are free to perform other tasks, thus improving system throughput, and preventing the accumulation of data element errors in the memory.
Inventors
- 👤 Glenn Dearth
- 👤 Thomas D. Bissett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:37
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/106
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
191 words
A method of operating a computer system comprising at least one central processing unit and at least one direct memory access controller comprising the steps of: at least one requesting device transmitting at least one request signal for access to certain ones of a plurality of addressable memory locations; and in response to said at least one request signal performing the steps including; A) using said direct memory access controller to transfer a plurality of data elements and associated check bits stored in a corresponding plurality of said addressable memory locations, to said requesting device; B) using the associated check bit data of each of said plurality of data elements to detect the occurrence of an error in each of said plurality of data elements; C) recording the memory address of a first of said plurality of data elements for which an error is detected; D) using said direct memory access controller to read data from the memory address for which said error was detected; E) correcting said data using said direct memory access controller, to provide a corrected data element; and F) storing said corrected data element in said memory.
Claim 2
Independent Claim
191 words
A method of operating a computer system comprising at least one central processing unit and at least one direct memory access controller comprising the steps of: at least one requesting device transmitting at least one request signal for access to certain ones of a plurality of addressable memory locations; and in response to said at least one request signal performing the steps including; A) using said direct memory access controller to transfer a plurality of data elements and associated check bits stored in a corresponding plurality of said addressable memory locations, to said requesting device; B) using the associated check bit data of each of said plurality of data elements to detect the occurrence of an error in each of said plurality of data elements; C) recording the memory address of a first of said plurality of data elements for which an error is detected; D) using said direct memory access controller to read data from the memory address for which said error was detected; E) correcting said data using said direct memory access controller, to provide a corrected data element; and F) storing said corrected data element in said memory.
Claim 3
Dependent Claim
38 words
The method as recited in claim 1 wherein said step of using said direct memory access controller to read the data for which said error was detected, occurs after said transfer of the block of memory is completed.
Claim 4
Dependent Claim
37 words
The method as recited in claim 2 wherein said method further comprises the step of: sending a request from said central processing unit to said direct memory access controller, initiating said transfer of said block of data.
Claim 5
Dependent Claim
32 words
The method as recited in claim 3 further comprising the step of: transferring said block of data without said central processing unit exercising control over said transfer of said block of data.
Claim 6
Dependent Claim
41 words
The method as recited in claim 4 wherein said step of using said direct memory access controller to read said data from the memory address for which said error was detected is not under the control of said central processing unit.
Claim 7
Independent Claim
132 words
A method of operating a fault tolerant computer system comprises the steps of: using a direct memory access controller operating separately from a central processing unit for transferring a block of data elements and corresponding check bits from a memory device; using said direct memory access controller to check each data element in said block of data for the occurrence of an error in said data; storing the address of a data element for which an error was detected; using said direct memory access controller to transfer data elements from said address for which an error in said data element was detected and correct the error in said data to provide a corrected data element; and writing said corrected data element back to said memory location using said direct memory access controller.
Claim 8
Independent Claim
132 words
A method of operating a fault tolerant computer system comprises the steps of: using a direct memory access controller operating separately from a central processing unit for transferring a block of data elements and corresponding check bits from a memory device; using said direct memory access controller to check each data element in said block of data for the occurrence of an error in said data; storing the address of a data element for which an error was detected; using said direct memory access controller to transfer data elements from said address for which an error in said data element was detected and correct the error in said data to provide a corrected data element; and writing said corrected data element back to said memory location using said direct memory access controller.
Claim 9
Dependent Claim
38 words
The method as recited in claim 6 wherein said step of using said direct memory access controller to retransfer the data for which an error was detected, occurs after said transfer of the block of memory is completed.
Claim 10
Dependent Claim
37 words
The method as recited in claim 6 wherein said method further comprises the step of: sending a request from said central processing unit to said direct memory access controller, initiating said transfer of said block of data.
Claim 11
Dependent Claim
33 words
The method as recited in claim 8 further comprising the step of: transferring said block of data using said direct memory access controller without said central processing unit exercising control over said transfer.
Claim 12
Independent Claim
140 words
An apparatus comprising: a central processing unit and a direct memory access (DMA) controller, said controller comprising: a storage register; and a plurality of registers with one of said plurality of registers coupled to said storage register, with said plurality of registers arranged in a pipelined delay of a corresponding number of clock periods related to the number of clock periods required for the DMA controller to complete processing of a signal indicating an error in reading a location in memory and to store in said storage register an address of a location in memory for which said error in data read from said location is detected; and means for reading from said storage register said location in memory, for correcting said error in data read from said location, and for writing said corrected data back to said memory location.
Claim 13
Independent Claim
140 words
An apparatus comprising: a central processing unit and a direct memory access (DMA) controller, said controller comprising: a storage register; and a plurality of registers with one of said plurality of registers coupled to said storage register, with said plurality of registers arranged in a pipelined delay of a corresponding number of clock periods related to the number of clock periods required for the DMA controller to complete processing of a signal indicating an error in reading a location in memory and to store in said storage register an address of a location in memory for which said error in data read from said location is detected; and means for reading from said storage register said location in memory, for correcting said error in data read from said location, and for writing said corrected data back to said memory location.
Claim 14
Dependent Claim
58 words
The apparatus as recited in claim 10 wherein said direct memory access (DMA) controller further comprises: means for holding said address in said storage means upon the detection of an error; and means for delaying said means for reading, correcting and writing said corrected data, until said DMA controller has completed a transfer of a block of data.
Claim 15
Dependent Claim
32 words
The apparatus as recited in claim 11 wherein said DMA controller further comprises: means for reading a block of data from a memory and for transferring said data to a requesting device.
Claim 16
Dependent Claim
59 words
The apparatus as recited in claim 12 further comprising: a central processing unit; a memory device; an input/output device; and a bus disposed to couple said central processing unit to said memory device and said input/output device; and wherein said data transfer of said DMA is initiated by said CPU but is not under the control of the CPU.
Claim 17
Dependent Claim
163 words
A fault tolerant computer comprising: a first computing zone comprising: a first direct memory access (DMA) controller, said first controller comprising: first means for storing an address of a location in memory for which an error in data read from said location is detected; first means for reading said location in memory, for correcting said error in data read from said location, and for writing said corrected data back to said memory location; a second computing zone, comprising a second direct memory access (DMA) controller, said second controller comprising: second means for storing an address of a location in memory for which an error in data read from said location is detected; second means for reading said location in memory, for correcting said error in data read from said location, and for writing said corrected data back to said memory location; and means for synchronizing the correction of the memory in the first zone with correction of the memory in the second zone.
Claim 18
Dependent Claim
163 words
A fault tolerant computer comprising: a first computing zone comprising: a first direct memory access (DMA) controller, said first controller comprising: first means for storing an address of a location in memory for which an error in data read from said location is detected; first means for reading said location in memory, for correcting said error in data read from said location, and for writing said corrected data back to said memory location; a second computing zone, comprising a second direct memory access (DMA) controller, said second controller comprising: second means for storing an address of a location in memory for which an error in data read from said location is detected; second means for reading said location in memory, for correcting said error in data read from said location, and for writing said corrected data back to said memory location; and means for synchronizing the correction of the memory in the first zone with correction of the memory in the second zone.
Claim 19
Dependent Claim
60 words
The apparatus of claim 14 wherein said means for synchronizing comprises: means for providing a signal from a first one of said zones indicating whether an error has occured in data read from the DMA controller of said zone and for delaying said address with the error until said signal is processed in the other one of said two zones.
Claim 20
Dependent Claim
21 words
The apparatus as recited in claim 15 wherein said means for storing said location of the detected error is a register.
Claim 21
Dependent Claim
80 words
The apparatus as recited in claim 16 wherein said register is a storage register and wherein said means for delaying further comprises: a plurality of registers including said storage register, with said registers arranged in a pipelined delay of a corresponding number of clock periods related to the number of clock periods required for the DMA controller to complete processing of an error signal of a location in memory between each of the zones of the fault tolerant computer system.
Claim 22
Dependent Claim
57 words
The apparatus as recited in claim 17 wherein said direct memory access controller further comprises: means for holding said address in said storage means upon the detection of an error; means for delaying said means for reading, correcting and writing said corrected data, until said first and second DMA controllers have completed transfers of blocks of data.
Claim 23
Dependent Claim
34 words
The apparatus as recited in claim 18 wherein each of said DMA controllers further comprises: means for reading a block of data from a memory and for transferring said data to a requesting device.
Claim 24
Dependent Claim
62 words
The apparatus as recited in claim 19 wherein each zone further comprises: a central processing unit; a memory device; an input/output device; and a bus disposed to couple said central processing unit to said memory device and said input/output device; and wherein said data transfer of said DMA is initiated by said CPU but is not under the control of the CPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |