Real time cache implemented by on-chip memory having standard and cache operating modes

Abstract

Abstract An integrated circuit chip includes a processor (4) and a memory (10) coupled by data and address buses (PAB, PDB). The memory is switchable between a first, standard, mode of operation in which a memory controller (14) is operative and a second, cache, mode of operation in which a cache controller (12) is operative by a switch (16, 22, 40). A memory area includes a valid bits array (VBA), a bit of which is set when a valid word is stored in a respective memory address of the memory in standard mode. If a valid bit exists corresponding to an address on the address bus, then information loaded into the memory in standard mode can be used by the processor in cache mode. The operating mode of the memory is switched using an operating mode register having a cache enable section, and a cache enable control line coupled to the memory. A reset arrangement is provided for resetting the valid bits array to flush the cache in a single operation. In one preferred embodiment, the cache is an instruction cache and the integrated circuit chip is a digital signal processor (DSP).

Inventors

• 👤 Nathan Baron
• 👤 Paul Marino
• 👤 Avner Goren
• 👤 Eyal Melanmed-Cohen

Bibliographic Details