US5586078A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic type memory
Assignee: Toshiba Corp
•
Filing: 1995-09-14
•
Granted: 1996-12-17
•
Expires: 2015-09-14
Abstract
Abstract A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.
Inventors
- 👤 Satoru Takase
- 👤 Kiyofumi Sakurai
- 👤 Masaki Ogihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4096
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
278 words
A dynamic type memory of a shared sense amplifier structure comprising: a plurality of memory cell blocks arranged in a first direction on a semiconductor chip, each constituting a memory cell bank and including a plurality of sub arrays of a memory cell array and a plurality of sense amplifiers used as cache memories, the sub arrays and the sense amplifiers being alternately arranged in a second direction perpendicular to said first direction, with one of the sense amplifiers being on each end of an arrangement of the sub arrays and the sense amplifiers, each of said sub arrays having a plurality of dynamic type memory cells arranged in a matrix, a plurality of word lines each connected to those of the memory cells which are in a row and a plurality of bit lines each connected to those of the memory cells which are in a column, each of the sense amplifiers including a plurality of amplifier circuits connected to the bit lines, each of the amplifier circuits for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected; a plurality of data lines provided to said sub arrays, the data lines being arranged on said semiconductor chip and extending in said first direction, each of the data lines for transferring data sensed and amplified by an amplifier circuit of a sense amplifier of a corresponding sub array; and a plurality of input/output pads provided to the sub arrays of the banks, the input/output pads being in an arrangement in said second direction on said semiconductor chip, the arrangement being located on one side of said memory cell array.
Claim 2
Dependent Claim
278 words
A dynamic type memory of a shared sense amplifier structure comprising: a plurality of memory cell blocks arranged in a first direction on a semiconductor chip, each constituting a memory cell bank and including a plurality of sub arrays of a memory cell array and a plurality of sense amplifiers used as cache memories, the sub arrays and the sense amplifiers being alternately arranged in a second direction perpendicular to said first direction, with one of the sense amplifiers being on each end of an arrangement of the sub arrays and the sense amplifiers, each of said sub arrays having a plurality of dynamic type memory cells arranged in a matrix, a plurality of word lines each connected to those of the memory cells which are in a row and a plurality of bit lines each connected to those of the memory cells which are in a column, each of the sense amplifiers including a plurality of amplifier circuits connected to the bit lines, each of the amplifier circuits for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected; a plurality of data lines provided to said sub arrays, the data lines being arranged on said semiconductor chip and extending in said first direction, each of the data lines for transferring data sensed and amplified by an amplifier circuit of a sense amplifier of a corresponding sub array; and a plurality of input/output pads provided to the sub arrays of the banks, the input/output pads being in an arrangement in said second direction on said semiconductor chip, the arrangement being located on one side of said memory cell array.
Claim 3
Dependent Claim
116 words
A dynamic type memory according to claim 1, further comprising a plurality of data buffer circuits provided to the sub arrays of said memory blocks, each for amplifying data transferred via a corresponding data line of a corresponding sub array, the data buffer circuits being in an arrangement in said second direction on said semiconductor chip and a plurality of multiplexers being in an arrangement in said second direction on said semiconductor chip, the arrangement of the multiplexers being between said arrangement of the input/output pads and the arrangement of the data buffer circuits which are closest to input/output pads, each of the multiplexers being connected to a corresponding sub array of each of said banks.
Claim 4
Dependent Claim
57 words
A dynamic type memory according to claim 1, further comprising a plurality of data buffer and multiplexer circuits arranged in said second direction on said semiconductor chip, an arrangement of said data buffer and multiplexer circuits being between said arrangement of the input/output pads and that of said memory blocks which are closest to the input/output pads.
Claim 5
Dependent Claim
51 words
A dynamic type memory according to claim 1, wherein those of said data lines which are provided to the sub arrays of one of said memory blocks are arranged over the sense amplifiers of another of said memory blocks which is nearer to said input/output pads than said one memory block.
Claim 6
Dependent Claim
51 words
A dynamic type memory according to claim 2, wherein those of said data lines which are provided to the sub arrays of one of said memory blocks are arranged over the sense amplifiers of another of said memory blocks which is nearer to said input/output pads than said one memory block.
Claim 7
Dependent Claim
51 words
A dynamic type memory according to claim 3, wherein those of said data lines which are provided to the sub arrays of one of said memory blocks are arranged over the sense amplifiers of another of said memory blocks which is nearer to said input/output pads than said one memory block.
Claim 8
Dependent Claim
63 words
A dynamic type memory according to claim 1, wherein those of said data lines which are provided to the sub arrays of one of said memory blocks have a size larger than that of those of the data lines which are provided for sub arrays of another of said memory blocks which is nearer to said input/output pads than said one memory block.
Claim 9
Dependent Claim
63 words
A dynamic type memory according to claim 2, wherein those of said data lines which are provided to the sub arrays of one of said memory blocks have a size larger than that of those of the data lines which are provided for sub arrays of another of said memory blocks which is nearer to said input/output pads than said one memory block.
Claim 10
Dependent Claim
63 words
A dynamic type memory according to claim 3, wherein those of said data lines which are provided to the sub arrays of one of said memory blocks have a size larger than that of those of the data lines which are provided for sub arrays of another of said memory blocks which is nearer to said input/output pads than said one memory block.
Claim 11
Dependent Claim
29 words
A dynamic type memory according to claim 1, wherein each of the sense amplifiers is shared in a time division manner by two of the sub arrays adjacent thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |